target/linux/generic-2.6/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366rb.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  24 #define RTL8366RB_DRIVER_VER    "0.2.2"
  25
  26 #define RTL8366RB_PHY_NO_MAX    4
  27 #define RTL8366RB_PHY_PAGE_MAX  7
  28 #define RTL8366RB_PHY_ADDR_MAX  31
  29
  30 /* Switch Global Configuration register */
  31 #define RTL8366RB_SGCR                          0x0000
  32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  33 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  35 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  36 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  38 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  39 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  40 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  41
  42 /* Port Enable Control register */
  43 #define RTL8366RB_PECR                          0x0001
  44
  45 /* Switch Security Control registers */
  46 #define RTL8366RB_SSCR0                         0x0002
  47 #define RTL8366RB_SSCR1                         0x0003
  48 #define RTL8366RB_SSCR2                         0x0004
  49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  50
  51 #define RTL8366RB_RESET_CTRL_REG                0x0100
  52 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  53 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  54
  55 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  56 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  57 #define RTL8366RB_CHIP_ID_REG                   0x0509
  58 #define RTL8366RB_CHIP_ID_8366                  0x5937
  59
  60 /* PHY registers control */
  61 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  62 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  63
  64 #define RTL8366RB_PHY_CTRL_READ                 1
  65 #define RTL8366RB_PHY_CTRL_WRITE                0
  66
  67 #define RTL8366RB_PHY_REG_MASK                  0x1f
  68 #define RTL8366RB_PHY_PAGE_OFFSET               5
  69 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  70 #define RTL8366RB_PHY_NO_OFFSET                 9
  71 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  72
  73 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
  74
  75 /* LED control registers */
  76 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  77 #define RTL8366RB_LED_BLINKRATE_BIT             0
  78 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  79
  80 #define RTL8366RB_LED_CTRL_REG                  0x0431
  81 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  82 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  83
  84 #define RTL8366RB_MIB_COUNT                     33
  85 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  86 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  87 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  88 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  89 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  90 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  91 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  92 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  93 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  94
  95 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
  96 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
  97                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
  98 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
  99 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 100
 101
 102 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 103 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 104
 105
 106 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 107 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 108 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 109
 110 #define RTL8366RB_VLAN_MEMCONF_BASE             0x0020
 111
 112
 113 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 114 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 115 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 116 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 117 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 118 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 119 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 120
 121
 122 #define RTL8366RB_PORT_NUM_CPU          5
 123 #define RTL8366RB_NUM_PORTS             6
 124 #define RTL8366RB_NUM_VLANS             16
 125 #define RTL8366RB_NUM_LEDGROUPS         4
 126 #define RTL8366RB_NUM_VIDS              4096
 127 #define RTL8366RB_PRIORITYMAX           7
 128 #define RTL8366RB_FIDMAX                7
 129
 130
 131 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 132 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 133 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 134 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 135 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 136
 137 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 138
 139 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 140                                          RTL8366RB_PORT_2 |     \
 141                                          RTL8366RB_PORT_3 |     \
 142                                          RTL8366RB_PORT_4 |     \
 143                                          RTL8366RB_PORT_5 |     \
 144                                          RTL8366RB_PORT_CPU)
 145
 146 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 147                                          RTL8366RB_PORT_2 |     \
 148                                          RTL8366RB_PORT_3 |     \
 149                                          RTL8366RB_PORT_4 |     \
 150                                          RTL8366RB_PORT_5)
 151
 152 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 153                                          RTL8366RB_PORT_2 |     \
 154                                          RTL8366RB_PORT_3 |     \
 155                                          RTL8366RB_PORT_4)
 156
 157 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 158
 159 struct rtl8366rb {
 160         struct device           *parent;
 161         struct rtl8366_smi      smi;
 162         struct switch_dev       dev;
 163 };
 164
 165 struct rtl8366rb_vlan_mc {
 166         u16     reserved2:1;
 167         u16     priority:3;
 168         u16     vid:12;
 169         u16     untag:8;
 170         u16     member:8;
 171         u16     stag_mbr:8;
 172         u16     stag_idx:3;
 173         u16     reserved1:2;
 174         u16     fid:3;
 175 };
 176
 177 struct rtl8366rb_vlan_4k {
 178         u16     reserved1:4;
 179         u16     vid:12;
 180         u16     untag:8;
 181         u16     member:8;
 182         u16     reserved2:13;
 183         u16     fid:3;
 184 };
 185
 186 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 187         { 0,  0, 4, "IfInOctets"                                },
 188         { 0,  4, 4, "EtherStatsOctets"                          },
 189         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 190         { 0, 10, 2, "EtherFragments"                            },
 191         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 192         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 193         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 194         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 195         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 196         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 197         { 0, 24, 2, "EtherOversizeStats"                        },
 198         { 0, 26, 2, "EtherStatsJabbers"                         },
 199         { 0, 28, 2, "IfInUcastPkts"                             },
 200         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 201         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 202         { 0, 34, 2, "EtherStatsDropEvents"                      },
 203         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 204         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 205         { 0, 40, 2, "Dot3InPauseFrames"                         },
 206         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 207         { 0, 44, 4, "IfOutOctets"                               },
 208         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 209         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 210         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 211         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 212         { 0, 56, 2, "EtherStatsCollisions"                      },
 213         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 214         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 215         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 216         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 217         { 0, 66, 2, "IfOutUcastPkts"                            },
 218         { 0, 68, 2, "IfOutMulticastPkts"                        },
 219         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 220 };
 221
 222 #define REG_WR(_smi, _reg, _val)                                        \
 223         do {                                                            \
 224                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 225                 if (err)                                                \
 226                         return err;                                     \
 227         } while (0)
 228
 229 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 230         do {                                                            \
 231                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 232                 if (err)                                                \
 233                         return err;                                     \
 234         } while (0)
 235
 236 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
 237 {
 238         return container_of(smi, struct rtl8366rb, smi);
 239 }
 240
 241 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
 242 {
 243         return container_of(sw, struct rtl8366rb, dev);
 244 }
 245
 246 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 247 {
 248         struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
 249         return &rtl->smi;
 250 }
 251
 252 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 253 {
 254         int timeout = 10;
 255         u32 data;
 256
 257         rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
 258                               RTL8366RB_CHIP_CTRL_RESET_HW);
 259         do {
 260                 msleep(1);
 261                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 262                         return -EIO;
 263
 264                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 265                         break;
 266         } while (--timeout);
 267
 268         if (!timeout) {
 269                 printk("Timeout waiting for the switch to reset\n");
 270                 return -EIO;
 271         }
 272
 273         return 0;
 274 }
 275
 276 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
 277 {
 278         int err;
 279
 280         /* set maximum packet length to 1536 bytes */
 281         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 282                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 283
 284         /* enable all ports */
 285         REG_WR(smi, RTL8366RB_PECR, 0);
 286
 287         /* enable learning for all ports */
 288         REG_WR(smi, RTL8366RB_SSCR0, 0);
 289
 290         /* enable auto ageing for all ports */
 291         REG_WR(smi, RTL8366RB_SSCR1, 0);
 292
 293         /*
 294          * discard VLAN tagged packets if the port is not a member of
 295          * the VLAN with which the packets is associated.
 296          */
 297         REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
 298
 299         /* don't drop packets whose DA has not been learned */
 300         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 301
 302         return 0;
 303 }
 304
 305 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 306                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 307 {
 308         u32 reg;
 309         int ret;
 310
 311         if (phy_no > RTL8366RB_PHY_NO_MAX)
 312                 return -EINVAL;
 313
 314         if (page > RTL8366RB_PHY_PAGE_MAX)
 315                 return -EINVAL;
 316
 317         if (addr > RTL8366RB_PHY_ADDR_MAX)
 318                 return -EINVAL;
 319
 320         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 321                                     RTL8366RB_PHY_CTRL_READ);
 322         if (ret)
 323                 return ret;
 324
 325         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 326               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 327               (addr & RTL8366RB_PHY_REG_MASK);
 328
 329         ret = rtl8366_smi_write_reg(smi, reg, 0);
 330         if (ret)
 331                 return ret;
 332
 333         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 334         if (ret)
 335                 return ret;
 336
 337         return 0;
 338 }
 339
 340 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 341                                   u32 phy_no, u32 page, u32 addr, u32 data)
 342 {
 343         u32 reg;
 344         int ret;
 345
 346         if (phy_no > RTL8366RB_PHY_NO_MAX)
 347                 return -EINVAL;
 348
 349         if (page > RTL8366RB_PHY_PAGE_MAX)
 350                 return -EINVAL;
 351
 352         if (addr > RTL8366RB_PHY_ADDR_MAX)
 353                 return -EINVAL;
 354
 355         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 356                                     RTL8366RB_PHY_CTRL_WRITE);
 357         if (ret)
 358                 return ret;
 359
 360         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 361               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 362               (addr & RTL8366RB_PHY_REG_MASK);
 363
 364         ret = rtl8366_smi_write_reg(smi, reg, data);
 365         if (ret)
 366                 return ret;
 367
 368         return 0;
 369 }
 370
 371 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
 372                                      int port, unsigned long long *val)
 373 {
 374         int i;
 375         int err;
 376         u32 addr, data;
 377         u64 mibvalue;
 378
 379         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 380                 return -EINVAL;
 381
 382         addr = RTL8366RB_MIB_COUNTER_BASE +
 383                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 384                rtl8366rb_mib_counters[counter].offset;
 385
 386         /*
 387          * Writing access counter address first
 388          * then ASIC will prepare 64bits counter wait for being retrived
 389          */
 390         data = 0; /* writing data will be discard by ASIC */
 391         err = rtl8366_smi_write_reg(smi, addr, data);
 392         if (err)
 393                 return err;
 394
 395         /* read MIB control register */
 396         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 397         if (err)
 398                 return err;
 399
 400         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 401                 return -EBUSY;
 402
 403         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 404                 return -EIO;
 405
 406         mibvalue = 0;
 407         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 408                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 409                 if (err)
 410                         return err;
 411
 412                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 413         }
 414
 415         *val = mibvalue;
 416         return 0;
 417 }
 418
 419 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 420                                  struct rtl8366_vlan_4k *vlan4k)
 421 {
 422         struct rtl8366rb_vlan_4k vlan4k_priv;
 423         int err;
 424         u32 data;
 425         u16 *tableaddr;
 426
 427         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 428         vlan4k_priv.vid = vid;
 429
 430         if (vid >= RTL8366RB_NUM_VIDS)
 431                 return -EINVAL;
 432
 433         tableaddr = (u16 *)&vlan4k_priv;
 434
 435         /* write VID */
 436         data = *tableaddr;
 437         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
 438         if (err)
 439                 return err;
 440
 441         /* write table access control word */
 442         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 443                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 444         if (err)
 445                 return err;
 446
 447         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
 448         if (err)
 449                 return err;
 450
 451         *tableaddr = data;
 452         tableaddr++;
 453
 454         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
 455                                    &data);
 456         if (err)
 457                 return err;
 458
 459         *tableaddr = data;
 460         tableaddr++;
 461
 462         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
 463                                    &data);
 464         if (err)
 465                 return err;
 466         *tableaddr = data;
 467
 468         vlan4k->vid = vid;
 469         vlan4k->untag = vlan4k_priv.untag;
 470         vlan4k->member = vlan4k_priv.member;
 471         vlan4k->fid = vlan4k_priv.fid;
 472
 473         return 0;
 474 }
 475
 476 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 477                                  const struct rtl8366_vlan_4k *vlan4k)
 478 {
 479         struct rtl8366rb_vlan_4k vlan4k_priv;
 480         int err;
 481         u32 data;
 482         u16 *tableaddr;
 483
 484         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 485             vlan4k->member > RTL8366RB_PORT_ALL ||
 486             vlan4k->untag > RTL8366RB_PORT_ALL ||
 487             vlan4k->fid > RTL8366RB_FIDMAX)
 488                 return -EINVAL;
 489
 490         vlan4k_priv.vid = vlan4k->vid;
 491         vlan4k_priv.untag = vlan4k->untag;
 492         vlan4k_priv.member = vlan4k->member;
 493         vlan4k_priv.fid = vlan4k->fid;
 494
 495         tableaddr = (u16 *)&vlan4k_priv;
 496
 497         data = *tableaddr;
 498
 499         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
 500         if (err)
 501                 return err;
 502
 503         tableaddr++;
 504
 505         data = *tableaddr;
 506
 507         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
 508                                     data);
 509         if (err)
 510                 return err;
 511
 512         tableaddr++;
 513
 514         data = *tableaddr;
 515
 516         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
 517                                     data);
 518         if (err)
 519                 return err;
 520
 521         /* write table access control word */
 522         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 523                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 524
 525         return err;
 526 }
 527
 528 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 529                                  struct rtl8366_vlan_mc *vlanmc)
 530 {
 531         struct rtl8366rb_vlan_mc vlanmc_priv;
 532         int err;
 533         u32 addr;
 534         u32 data;
 535         u16 *tableaddr;
 536
 537         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 538
 539         if (index >= RTL8366RB_NUM_VLANS)
 540                 return -EINVAL;
 541
 542         tableaddr = (u16 *)&vlanmc_priv;
 543
 544         addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
 545         err = rtl8366_smi_read_reg(smi, addr, &data);
 546         if (err)
 547                 return err;
 548
 549         *tableaddr = data;
 550         tableaddr++;
 551
 552         addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
 553         err = rtl8366_smi_read_reg(smi, addr, &data);
 554         if (err)
 555                 return err;
 556
 557         *tableaddr = data;
 558         tableaddr++;
 559
 560         addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
 561         err = rtl8366_smi_read_reg(smi, addr, &data);
 562         if (err)
 563                 return err;
 564
 565         *tableaddr = data;
 566
 567         vlanmc->vid = vlanmc_priv.vid;
 568         vlanmc->priority = vlanmc_priv.priority;
 569         vlanmc->untag = vlanmc_priv.untag;
 570         vlanmc->member = vlanmc_priv.member;
 571         vlanmc->fid = vlanmc_priv.fid;
 572
 573         return 0;
 574 }
 575
 576 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 577                                  const struct rtl8366_vlan_mc *vlanmc)
 578 {
 579         struct rtl8366rb_vlan_mc vlanmc_priv;
 580         int err;
 581         u32 addr;
 582         u32 data;
 583         u16 *tableaddr;
 584
 585         if (index >= RTL8366RB_NUM_VLANS ||
 586             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 587             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 588             vlanmc->member > RTL8366RB_PORT_ALL ||
 589             vlanmc->untag > RTL8366RB_PORT_ALL ||
 590             vlanmc->fid > RTL8366RB_FIDMAX)
 591                 return -EINVAL;
 592
 593         vlanmc_priv.vid = vlanmc->vid;
 594         vlanmc_priv.priority = vlanmc->priority;
 595         vlanmc_priv.untag = vlanmc->untag;
 596         vlanmc_priv.member = vlanmc->member;
 597         vlanmc_priv.stag_mbr = 0;
 598         vlanmc_priv.stag_idx = 0;
 599         vlanmc_priv.fid = vlanmc->fid;
 600
 601         addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
 602
 603         tableaddr = (u16 *)&vlanmc_priv;
 604         data = *tableaddr;
 605
 606         err = rtl8366_smi_write_reg(smi, addr, data);
 607         if (err)
 608                 return err;
 609
 610         addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
 611
 612         tableaddr++;
 613         data = *tableaddr;
 614
 615         err = rtl8366_smi_write_reg(smi, addr, data);
 616         if (err)
 617                 return err;
 618
 619         addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
 620
 621         tableaddr++;
 622         data = *tableaddr;
 623
 624         err = rtl8366_smi_write_reg(smi, addr, data);
 625         if (err)
 626                 return err;
 627         return 0;
 628 }
 629
 630 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 631 {
 632         u32 data;
 633         int err;
 634
 635         if (port >= RTL8366RB_NUM_PORTS)
 636                 return -EINVAL;
 637
 638         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 639                                    &data);
 640         if (err)
 641                 return err;
 642
 643         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 644                RTL8366RB_PORT_VLAN_CTRL_MASK;
 645
 646         return 0;
 647
 648 }
 649
 650 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 651 {
 652         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 653                 return -EINVAL;
 654
 655         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 656                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 657                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 658                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 659                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 660 }
 661
 662 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 663 {
 664         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
 665                                 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
 666 }
 667
 668 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 669 {
 670         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
 671                                 RTL8366RB_SGCR_EN_VLAN_4KTB,
 672                                 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
 673 }
 674
 675 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 676                                   const struct switch_attr *attr,
 677                                   struct switch_val *val)
 678 {
 679         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 680         int err = 0;
 681
 682         if (val->value.i == 1)
 683                 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 684                                        RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 685
 686         return err;
 687 }
 688
 689 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
 690                                        const struct switch_attr *attr,
 691                                        struct switch_val *val)
 692 {
 693         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 694         u32 data;
 695
 696         if (attr->ofs == 1) {
 697                 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 698
 699                 if (data & RTL8366RB_SGCR_EN_VLAN)
 700                         val->value.i = 1;
 701                 else
 702                         val->value.i = 0;
 703         } else if (attr->ofs == 2) {
 704                 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 705
 706                 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
 707                         val->value.i = 1;
 708                 else
 709                         val->value.i = 0;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 716                                      const struct switch_attr *attr,
 717                                      struct switch_val *val)
 718 {
 719         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 720         u32 data;
 721
 722         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 723
 724         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 725
 726         return 0;
 727 }
 728
 729 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 730                                     const struct switch_attr *attr,
 731                                     struct switch_val *val)
 732 {
 733         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 734
 735         if (val->value.i >= 6)
 736                 return -EINVAL;
 737
 738         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 739                                 RTL8366RB_LED_BLINKRATE_MASK,
 740                                 val->value.i);
 741 }
 742
 743 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
 744                                        const struct switch_attr *attr,
 745                                        struct switch_val *val)
 746 {
 747         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 748
 749         if (attr->ofs == 1)
 750                 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
 751         else
 752                 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
 753 }
 754
 755 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
 756                                        const struct switch_attr *attr,
 757                                        struct switch_val *val)
 758 {
 759         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 760         u32 data;
 761
 762         rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
 763         val->value.i = !data;
 764
 765         return 0;
 766 }
 767
 768
 769 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
 770                                        const struct switch_attr *attr,
 771                                        struct switch_val *val)
 772 {
 773         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 774         u32 portmask = 0;
 775         int err = 0;
 776
 777         if (!val->value.i)
 778                 portmask = RTL8366RB_PORT_ALL;
 779
 780         /* set learning for all ports */
 781         REG_WR(smi, RTL8366RB_SSCR0, portmask);
 782
 783         /* set auto ageing for all ports */
 784         REG_WR(smi, RTL8366RB_SSCR1, portmask);
 785
 786         return 0;
 787 }
 788
 789
 790 static const char *rtl8366rb_speed_str(unsigned speed)
 791 {
 792         switch (speed) {
 793         case 0:
 794                 return "10baseT";
 795         case 1:
 796                 return "100baseT";
 797         case 2:
 798                 return "1000baseT";
 799         }
 800
 801         return "unknown";
 802 }
 803
 804 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 805                                      const struct switch_attr *attr,
 806                                      struct switch_val *val)
 807 {
 808         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 809         u32 len = 0, data = 0;
 810
 811         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 812                 return -EINVAL;
 813
 814         memset(smi->buf, '\0', sizeof(smi->buf));
 815         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
 816                              (val->port_vlan / 2), &data);
 817
 818         if (val->port_vlan % 2)
 819                 data = data >> 8;
 820
 821         if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
 822                 len = snprintf(smi->buf, sizeof(smi->buf),
 823                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 824                                 val->port_vlan,
 825                                 rtl8366rb_speed_str(data &
 826                                           RTL8366RB_PORT_STATUS_SPEED_MASK),
 827                                 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
 828                                         "full" : "half",
 829                                 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
 830                                         "tx-pause ": "",
 831                                 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
 832                                         "rx-pause " : "",
 833                                 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
 834                                         "nway ": "");
 835         } else {
 836                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 837                                 val->port_vlan);
 838         }
 839
 840         val->value.s = smi->buf;
 841         val->len = len;
 842
 843         return 0;
 844 }
 845
 846 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
 847                                      const struct switch_attr *attr,
 848                                      struct switch_val *val)
 849 {
 850         int i;
 851         u32 len = 0;
 852         struct rtl8366_vlan_4k vlan4k;
 853         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 854         char *buf = smi->buf;
 855         int err;
 856
 857         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 858                 return -EINVAL;
 859
 860         memset(buf, '\0', sizeof(smi->buf));
 861
 862         err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 863         if (err)
 864                 return err;
 865
 866         len += snprintf(buf + len, sizeof(smi->buf) - len,
 867                         "VLAN %d: Ports: '", vlan4k.vid);
 868
 869         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 870                 if (!(vlan4k.member & (1 << i)))
 871                         continue;
 872
 873                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 874                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 875         }
 876
 877         len += snprintf(buf + len, sizeof(smi->buf) - len,
 878                         "', members=%04x, untag=%04x, fid=%u",
 879                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 880
 881         val->value.s = buf;
 882         val->len = len;
 883
 884         return 0;
 885 }
 886
 887 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 888                                     const struct switch_attr *attr,
 889                                     struct switch_val *val)
 890 {
 891         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 892         u32 data;
 893         u32 mask;
 894         u32 reg;
 895
 896         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 897                 return -EINVAL;
 898
 899         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 900                 reg = RTL8366RB_LED_BLINKRATE_REG;
 901                 mask = 0xF << 4;
 902                 data = val->value.i << 4;
 903         } else {
 904                 reg = RTL8366RB_LED_CTRL_REG;
 905                 mask = 0xF << (val->port_vlan * 4),
 906                 data = val->value.i << (val->port_vlan * 4);
 907         }
 908
 909         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
 910 }
 911
 912 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 913                                     const struct switch_attr *attr,
 914                                     struct switch_val *val)
 915 {
 916         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 917         u32 data = 0;
 918
 919         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 920                 return -EINVAL;
 921
 922         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 923         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 924
 925         return 0;
 926 }
 927
 928 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 929                                        const struct switch_attr *attr,
 930                                        struct switch_val *val)
 931 {
 932         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 933
 934         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 935                 return -EINVAL;
 936
 937         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 938                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 939 }
 940
 941 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
 942                                     const struct switch_attr *attr,
 943                                     struct switch_val *val)
 944 {
 945         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 946         int i, len = 0;
 947         unsigned long long counter = 0;
 948         char *buf = smi->buf;
 949
 950         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 951                 return -EINVAL;
 952
 953         len += snprintf(buf + len, sizeof(smi->buf) - len,
 954                         "Port %d MIB counters\n",
 955                         val->port_vlan);
 956
 957         for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
 958                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 959                                 "%-36s: ", rtl8366rb_mib_counters[i].name);
 960                 if (!rtl8366rb_get_mib_counter(smi, i, val->port_vlan, &counter))
 961                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 962                                         "%llu\n", counter);
 963                 else
 964                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 965                                         "%s\n", "error");
 966         }
 967
 968         val->value.s = buf;
 969         val->len = len;
 970         return 0;
 971 }
 972
 973 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
 974                                       struct switch_val *val)
 975 {
 976         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 977         struct switch_port *port;
 978         struct rtl8366_vlan_4k vlan4k;
 979         int i;
 980
 981         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 982                 return -EINVAL;
 983
 984         rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 985
 986         port = &val->value.ports[0];
 987         val->len = 0;
 988         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 989                 if (!(vlan4k.member & BIT(i)))
 990                         continue;
 991
 992                 port->id = i;
 993                 port->flags = (vlan4k.untag & BIT(i)) ?
 994                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
 995                 val->len++;
 996                 port++;
 997         }
 998         return 0;
 999 }
1000
1001 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1002                                       struct switch_val *val)
1003 {
1004         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1005         struct switch_port *port;
1006         u32 member = 0;
1007         u32 untag = 0;
1008         int i;
1009
1010         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1011                 return -EINVAL;
1012
1013         port = &val->value.ports[0];
1014         for (i = 0; i < val->len; i++, port++) {
1015                 member |= BIT(port->id);
1016
1017                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1018                         untag |= BIT(port->id);
1019         }
1020
1021         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1022 }
1023
1024 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1025 {
1026         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1027         return rtl8366_get_pvid(smi, port, val);
1028 }
1029
1030 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1031 {
1032         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1033         return rtl8366_set_pvid(smi, port, val);
1034 }
1035
1036 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1037 {
1038         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1039         int err;
1040
1041         err = rtl8366rb_reset_chip(smi);
1042         if (err)
1043                 return err;
1044
1045         err = rtl8366rb_hw_init(smi);
1046         if (err)
1047                 return err;
1048
1049         return rtl8366_reset_vlan(smi);
1050 }
1051
1052 static struct switch_attr rtl8366rb_globals[] = {
1053         {
1054                 .type = SWITCH_TYPE_INT,
1055                 .name = "enable_learning",
1056                 .description = "Enable learning, enable aging",
1057                 .set = rtl8366rb_sw_set_learning_enable,
1058                 .get = rtl8366rb_sw_get_learning_enable,
1059                 .max = 1
1060         }, {
1061                 .type = SWITCH_TYPE_INT,
1062                 .name = "enable_vlan",
1063                 .description = "Enable VLAN mode",
1064                 .set = rtl8366rb_sw_set_vlan_enable,
1065                 .get = rtl8366rb_sw_get_vlan_enable,
1066                 .max = 1,
1067                 .ofs = 1
1068         }, {
1069                 .type = SWITCH_TYPE_INT,
1070                 .name = "enable_vlan4k",
1071                 .description = "Enable VLAN 4K mode",
1072                 .set = rtl8366rb_sw_set_vlan_enable,
1073                 .get = rtl8366rb_sw_get_vlan_enable,
1074                 .max = 1,
1075                 .ofs = 2
1076         }, {
1077                 .type = SWITCH_TYPE_INT,
1078                 .name = "reset_mibs",
1079                 .description = "Reset all MIB counters",
1080                 .set = rtl8366rb_sw_reset_mibs,
1081                 .get = NULL,
1082                 .max = 1
1083         }, {
1084                 .type = SWITCH_TYPE_INT,
1085                 .name = "blinkrate",
1086                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1087                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1088                 .set = rtl8366rb_sw_set_blinkrate,
1089                 .get = rtl8366rb_sw_get_blinkrate,
1090                 .max = 5
1091         },
1092 };
1093
1094 static struct switch_attr rtl8366rb_port[] = {
1095         {
1096                 .type = SWITCH_TYPE_STRING,
1097                 .name = "link",
1098                 .description = "Get port link information",
1099                 .max = 1,
1100                 .set = NULL,
1101                 .get = rtl8366rb_sw_get_port_link,
1102         }, {
1103                 .type = SWITCH_TYPE_INT,
1104                 .name = "reset_mib",
1105                 .description = "Reset single port MIB counters",
1106                 .max = 1,
1107                 .set = rtl8366rb_sw_reset_port_mibs,
1108                 .get = NULL,
1109         }, {
1110                 .type = SWITCH_TYPE_STRING,
1111                 .name = "mib",
1112                 .description = "Get MIB counters for port",
1113                 .max = 33,
1114                 .set = NULL,
1115                 .get = rtl8366rb_sw_get_port_mib,
1116         }, {
1117                 .type = SWITCH_TYPE_INT,
1118                 .name = "led",
1119                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1120                 .max = 15,
1121                 .set = rtl8366rb_sw_set_port_led,
1122                 .get = rtl8366rb_sw_get_port_led,
1123         },
1124 };
1125
1126 static struct switch_attr rtl8366rb_vlan[] = {
1127         {
1128                 .type = SWITCH_TYPE_STRING,
1129                 .name = "info",
1130                 .description = "Get vlan information",
1131                 .max = 1,
1132                 .set = NULL,
1133                 .get = rtl8366rb_sw_get_vlan_info,
1134         },
1135 };
1136
1137 /* template */
1138 static struct switch_dev rtl8366_switch_dev = {
1139         .name = "RTL8366S",
1140         .cpu_port = RTL8366RB_PORT_NUM_CPU,
1141         .ports = RTL8366RB_NUM_PORTS,
1142         .vlans = RTL8366RB_NUM_VLANS,
1143         .attr_global = {
1144                 .attr = rtl8366rb_globals,
1145                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1146         },
1147         .attr_port = {
1148                 .attr = rtl8366rb_port,
1149                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1150         },
1151         .attr_vlan = {
1152                 .attr = rtl8366rb_vlan,
1153                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1154         },
1155
1156         .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1157         .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1158         .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1159         .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1160         .reset_switch = rtl8366rb_sw_reset_switch,
1161 };
1162
1163 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1164 {
1165         struct switch_dev *dev = &rtl->dev;
1166         int err;
1167
1168         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1169         dev->priv = rtl;
1170         dev->devname = dev_name(rtl->parent);
1171
1172         err = register_switch(dev, NULL);
1173         if (err)
1174                 dev_err(rtl->parent, "switch registration failed\n");
1175
1176         return err;
1177 }
1178
1179 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1180 {
1181         unregister_switch(&rtl->dev);
1182 }
1183
1184 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1185 {
1186         struct rtl8366_smi *smi = bus->priv;
1187         u32 val = 0;
1188         int err;
1189
1190         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1191         if (err)
1192                 return 0xffff;
1193
1194         return val;
1195 }
1196
1197 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1198 {
1199         struct rtl8366_smi *smi = bus->priv;
1200         u32 t;
1201         int err;
1202
1203         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1204         /* flush write */
1205         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1206
1207         return err;
1208 }
1209
1210 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1211 {
1212         return (bus->read == rtl8366rb_mii_read &&
1213                 bus->write == rtl8366rb_mii_write);
1214 }
1215
1216 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1217 {
1218         struct rtl8366_smi *smi = &rtl->smi;
1219         int ret;
1220
1221         ret = rtl8366rb_reset_chip(smi);
1222         if (ret)
1223                 return ret;
1224
1225         ret = rtl8366rb_hw_init(smi);
1226         return ret;
1227 }
1228
1229 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1230 {
1231         u32 chip_id = 0;
1232         u32 chip_ver = 0;
1233         int ret;
1234
1235         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1236         if (ret) {
1237                 dev_err(smi->parent, "unable to read chip id\n");
1238                 return ret;
1239         }
1240
1241         switch (chip_id) {
1242         case RTL8366RB_CHIP_ID_8366:
1243                 break;
1244         default:
1245                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1246                 return -ENODEV;
1247         }
1248
1249         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1250                                    &chip_ver);
1251         if (ret) {
1252                 dev_err(smi->parent, "unable to read chip version\n");
1253                 return ret;
1254         }
1255
1256         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1257                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1258
1259         return 0;
1260 }
1261
1262 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1263         .detect         = rtl8366rb_detect,
1264         .mii_read       = rtl8366rb_mii_read,
1265         .mii_write      = rtl8366rb_mii_write,
1266
1267         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1268         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1269         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1270         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1271         .get_mc_index   = rtl8366rb_get_mc_index,
1272         .set_mc_index   = rtl8366rb_set_mc_index,
1273         .get_mib_counter = rtl8366rb_get_mib_counter,
1274 };
1275
1276 static int __init rtl8366rb_probe(struct platform_device *pdev)
1277 {
1278         static int rtl8366_smi_version_printed;
1279         struct rtl8366rb_platform_data *pdata;
1280         struct rtl8366rb *rtl;
1281         struct rtl8366_smi *smi;
1282         int err;
1283
1284         if (!rtl8366_smi_version_printed++)
1285                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1286                        " version " RTL8366RB_DRIVER_VER"\n");
1287
1288         pdata = pdev->dev.platform_data;
1289         if (!pdata) {
1290                 dev_err(&pdev->dev, "no platform data specified\n");
1291                 err = -EINVAL;
1292                 goto err_out;
1293         }
1294
1295         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1296         if (!rtl) {
1297                 dev_err(&pdev->dev, "no memory for private data\n");
1298                 err = -ENOMEM;
1299                 goto err_out;
1300         }
1301
1302         rtl->parent = &pdev->dev;
1303
1304         smi = &rtl->smi;
1305         smi->parent = &pdev->dev;
1306         smi->gpio_sda = pdata->gpio_sda;
1307         smi->gpio_sck = pdata->gpio_sck;
1308         smi->ops = &rtl8366rb_smi_ops;
1309         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1310         smi->num_ports = RTL8366RB_NUM_PORTS;
1311         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1312         smi->mib_counters = rtl8366rb_mib_counters;
1313         smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1314
1315         err = rtl8366_smi_init(smi);
1316         if (err)
1317                 goto err_free_rtl;
1318
1319         platform_set_drvdata(pdev, rtl);
1320
1321         err = rtl8366rb_setup(rtl);
1322         if (err)
1323                 goto err_clear_drvdata;
1324
1325         err = rtl8366rb_switch_init(rtl);
1326         if (err)
1327                 goto err_clear_drvdata;
1328
1329         return 0;
1330
1331  err_clear_drvdata:
1332         platform_set_drvdata(pdev, NULL);
1333         rtl8366_smi_cleanup(smi);
1334  err_free_rtl:
1335         kfree(rtl);
1336  err_out:
1337         return err;
1338 }
1339
1340 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1341 {
1342         if (!rtl8366rb_mii_bus_match(phydev->bus))
1343                 return -EINVAL;
1344
1345         return 0;
1346 }
1347
1348 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1349 {
1350         return 0;
1351 }
1352
1353 static struct phy_driver rtl8366rb_phy_driver = {
1354         .phy_id         = 0x001cc960,
1355         .name           = "Realtek RTL8366RB",
1356         .phy_id_mask    = 0x1ffffff0,
1357         .features       = PHY_GBIT_FEATURES,
1358         .config_aneg    = rtl8366rb_phy_config_aneg,
1359         .config_init    = rtl8366rb_phy_config_init,
1360         .read_status    = genphy_read_status,
1361         .driver         = {
1362                 .owner = THIS_MODULE,
1363         },
1364 };
1365
1366 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1367 {
1368         struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1369
1370         if (rtl) {
1371                 rtl8366rb_switch_cleanup(rtl);
1372                 platform_set_drvdata(pdev, NULL);
1373                 rtl8366_smi_cleanup(&rtl->smi);
1374                 kfree(rtl);
1375         }
1376
1377         return 0;
1378 }
1379
1380 static struct platform_driver rtl8366rb_driver = {
1381         .driver = {
1382                 .name           = RTL8366RB_DRIVER_NAME,
1383                 .owner          = THIS_MODULE,
1384         },
1385         .probe          = rtl8366rb_probe,
1386         .remove         = __devexit_p(rtl8366rb_remove),
1387 };
1388
1389 static int __init rtl8366rb_module_init(void)
1390 {
1391         int ret;
1392         ret = platform_driver_register(&rtl8366rb_driver);
1393         if (ret)
1394                 return ret;
1395
1396         ret = phy_driver_register(&rtl8366rb_phy_driver);
1397         if (ret)
1398                 goto err_platform_unregister;
1399
1400         return 0;
1401
1402  err_platform_unregister:
1403         platform_driver_unregister(&rtl8366rb_driver);
1404         return ret;
1405 }
1406 module_init(rtl8366rb_module_init);
1407
1408 static void __exit rtl8366rb_module_exit(void)
1409 {
1410         phy_driver_unregister(&rtl8366rb_phy_driver);
1411         platform_driver_unregister(&rtl8366rb_driver);
1412 }
1413 module_exit(rtl8366rb_module_exit);
1414
1415 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1416 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1417 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1418 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1419 MODULE_LICENSE("GPL v2");
1420 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);