target/linux/generic/patches-3.6/020-ssb_update.patch

   1 --- a/drivers/ssb/b43_pci_bridge.c
   2 +++ b/drivers/ssb/b43_pci_bridge.c
   3 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
   4         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
   5         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
   6         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
   7 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
   8         { 0, },
   9  };
  10  MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
  11 --- a/drivers/ssb/driver_chipcommon.c
  12 +++ b/drivers/ssb/driver_chipcommon.c
  13 @@ -4,6 +4,7 @@
  14   *
  15   * Copyright 2005, Broadcom Corporation
  16   * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  17 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
  18   *
  19   * Licensed under the GNU/GPL. See COPYING for details.
  20   */
  21 @@ -12,6 +13,7 @@
  22  #include <linux/ssb/ssb_regs.h>
  23  #include <linux/export.h>
  24  #include <linux/pci.h>
  25 +#include <linux/bcm47xx_wdt.h>
  26
  27  #include "ssb_private.h"
  28
  29 @@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
  30         cc->fast_pwrup_delay = tmp;
  31  }
  32
  33 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
  34 +{
  35 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
  36 +               return ssb_pmu_get_alp_clock(cc);
  37 +
  38 +       return 20000000;
  39 +}
  40 +
  41 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
  42 +{
  43 +       u32 nb;
  44 +
  45 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  46 +               if (cc->dev->id.revision < 26)
  47 +                       nb = 16;
  48 +               else
  49 +                       nb = (cc->dev->id.revision >= 37) ? 32 : 24;
  50 +       } else {
  51 +               nb = 28;
  52 +       }
  53 +       if (nb == 32)
  54 +               return 0xffffffff;
  55 +       else
  56 +               return (1 << nb) - 1;
  57 +}
  58 +
  59 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
  60 +{
  61 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
  62 +
  63 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
  64 +               return 0;
  65 +
  66 +       return ssb_chipco_watchdog_timer_set(cc, ticks);
  67 +}
  68 +
  69 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
  70 +{
  71 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
  72 +       u32 ticks;
  73 +
  74 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
  75 +               return 0;
  76 +
  77 +       ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
  78 +       return ticks / cc->ticks_per_ms;
  79 +}
  80 +
  81 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
  82 +{
  83 +       struct ssb_bus *bus = cc->dev->bus;
  84 +
  85 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  86 +                       /* based on 32KHz ILP clock */
  87 +                       return 32;
  88 +       } else {
  89 +               if (cc->dev->id.revision < 18)
  90 +                       return ssb_clockspeed(bus) / 1000;
  91 +               else
  92 +                       return ssb_chipco_alp_clock(cc) / 1000;
  93 +       }
  94 +}
  95 +
  96  void ssb_chipcommon_init(struct ssb_chipcommon *cc)
  97  {
  98         if (!cc->dev)
  99 @@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
 100         chipco_powercontrol_init(cc);
 101         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 102         calc_fast_powerup_delay(cc);
 103 +
 104 +       if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
 105 +               cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
 106 +               cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
 107 +       }
 108  }
 109
 110  void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 111 @@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
 112  }
 113
 114  /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 115 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 116 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 117  {
 118 -       /* instant NMI */
 119 -       chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 120 +       u32 maxt;
 121 +       enum ssb_clkmode clkmode;
 122 +
 123 +       maxt = ssb_chipco_watchdog_get_max_timer(cc);
 124 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 125 +               if (ticks == 1)
 126 +                       ticks = 2;
 127 +               else if (ticks > maxt)
 128 +                       ticks = maxt;
 129 +               chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
 130 +       } else {
 131 +               clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
 132 +               ssb_chipco_set_clockmode(cc, clkmode);
 133 +               if (ticks > maxt)
 134 +                       ticks = maxt;
 135 +               /* instant NMI */
 136 +               chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 137 +       }
 138 +       return ticks;
 139  }
 140
 141  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 142 @@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
 143                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 144                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 145                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 146 -                       /* Fixed ALP clock */
 147 -                       baud_base = 20000000;
 148 -                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 149 -                               /* FIXME: baud_base is different for devices with a PMU */
 150 -                               SSB_WARN_ON(1);
 151 -                       }
 152 +                       baud_base = ssb_chipco_alp_clock(cc);
 153                         div = 1;
 154                         if (ccrev >= 21) {
 155                                 /* Turn off UART clock before switching clocksource. */
 156 --- a/drivers/ssb/driver_chipcommon_pmu.c
 157 +++ b/drivers/ssb/driver_chipcommon_pmu.c
 158 @@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
 159                         chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
 160                 }
 161                 break;
 162 +       case 43222:
 163 +               break;
 164         default:
 165                 ssb_printk(KERN_ERR PFX
 166                            "ERROR: PLL init unknown for device %04X\n",
 167 @@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
 168                  min_msk = 0xCBB;
 169                  break;
 170         case 0x4322:
 171 +       case 43222:
 172                 /* We keep the default settings:
 173                  * min_msk = 0xCBB
 174                  * max_msk = 0x7FFFF
 175 @@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
 176  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
 177  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
 178
 179 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
 180 +{
 181 +       u32 crystalfreq;
 182 +       const struct pmu0_plltab_entry *e = NULL;
 183 +
 184 +       crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
 185 +                     SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
 186 +       e = pmu0_plltab_find_entry(crystalfreq);
 187 +       BUG_ON(!e);
 188 +       return e->freq * 1000;
 189 +}
 190 +
 191 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
 192 +{
 193 +       struct ssb_bus *bus = cc->dev->bus;
 194 +
 195 +       switch (bus->chip_id) {
 196 +       case 0x5354:
 197 +               ssb_pmu_get_alp_clock_clk0(cc);
 198 +       default:
 199 +               ssb_printk(KERN_ERR PFX
 200 +                          "ERROR: PMU alp clock unknown for device %04X\n",
 201 +                          bus->chip_id);
 202 +               return 0;
 203 +       }
 204 +}
 205 +
 206  u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
 207  {
 208         struct ssb_bus *bus = cc->dev->bus;
 209 --- a/drivers/ssb/driver_extif.c
 210 +++ b/drivers/ssb/driver_extif.c
 211 @@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
 212         *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
 213  }
 214
 215 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 216 -                                 u32 ticks)
 217 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 218  {
 219 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 220 +
 221 +       return ssb_extif_watchdog_timer_set(extif, ticks);
 222 +}
 223 +
 224 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 225 +{
 226 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 227 +       u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
 228 +
 229 +       ticks = ssb_extif_watchdog_timer_set(extif, ticks);
 230 +
 231 +       return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
 232 +}
 233 +
 234 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 235 +{
 236 +       if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
 237 +               ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
 238         extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
 239 +
 240 +       return ticks;
 241  }
 242
 243  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 244 --- a/drivers/ssb/driver_mipscore.c
 245 +++ b/drivers/ssb/driver_mipscore.c
 246 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
 247  {
 248         struct ssb_bus *bus = mcore->dev->bus;
 249
 250 -       if (bus->extif.dev)
 251 +       if (ssb_extif_available(&bus->extif))
 252                 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
 253 -       else if (bus->chipco.dev)
 254 +       else if (ssb_chipco_available(&bus->chipco))
 255                 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
 256         else
 257                 mcore->nr_serial_ports = 0;
 258 @@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
 259  {
 260         struct ssb_bus *bus = mcore->dev->bus;
 261
 262 -       mcore->flash_buswidth = 2;
 263 -       if (bus->chipco.dev) {
 264 -               mcore->flash_window = 0x1c000000;
 265 -               mcore->flash_window_size = 0x02000000;
 266 +       /* When there is no chipcommon on the bus there is 4MB flash */
 267 +       if (!ssb_chipco_available(&bus->chipco)) {
 268 +               mcore->pflash.present = true;
 269 +               mcore->pflash.buswidth = 2;
 270 +               mcore->pflash.window = SSB_FLASH1;
 271 +               mcore->pflash.window_size = SSB_FLASH1_SZ;
 272 +               return;
 273 +       }
 274 +
 275 +       /* There is ChipCommon, so use it to read info about flash */
 276 +       switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
 277 +       case SSB_CHIPCO_FLASHT_STSER:
 278 +       case SSB_CHIPCO_FLASHT_ATSER:
 279 +               pr_err("Serial flash not supported\n");
 280 +               break;
 281 +       case SSB_CHIPCO_FLASHT_PARA:
 282 +               pr_debug("Found parallel flash\n");
 283 +               mcore->pflash.present = true;
 284 +               mcore->pflash.window = SSB_FLASH2;
 285 +               mcore->pflash.window_size = SSB_FLASH2_SZ;
 286                 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
 287                                & SSB_CHIPCO_CFG_DS16) == 0)
 288 -                       mcore->flash_buswidth = 1;
 289 -       } else {
 290 -               mcore->flash_window = 0x1fc00000;
 291 -               mcore->flash_window_size = 0x00400000;
 292 +                       mcore->pflash.buswidth = 1;
 293 +               else
 294 +                       mcore->pflash.buswidth = 2;
 295 +               break;
 296         }
 297  }
 298
 299 @@ -211,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
 300         if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 301                 return ssb_pmu_get_cpu_clock(&bus->chipco);
 302
 303 -       if (bus->extif.dev) {
 304 +       if (ssb_extif_available(&bus->extif)) {
 305                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
 306 -       } else if (bus->chipco.dev) {
 307 +       } else if (ssb_chipco_available(&bus->chipco)) {
 308                 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
 309         } else
 310                 return 0;
 311 @@ -249,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
 312                 hz = 100000000;
 313         ns = 1000000000 / hz;
 314
 315 -       if (bus->extif.dev)
 316 +       if (ssb_extif_available(&bus->extif))
 317                 ssb_extif_timing_init(&bus->extif, ns);
 318 -       else if (bus->chipco.dev)
 319 +       else if (ssb_chipco_available(&bus->chipco))
 320                 ssb_chipco_timing_init(&bus->chipco, ns);
 321
 322         /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
 323 --- a/drivers/ssb/embedded.c
 324 +++ b/drivers/ssb/embedded.c
 325 @@ -4,11 +4,13 @@
 326   *
 327   * Copyright 2005-2008, Broadcom Corporation
 328   * Copyright 2006-2008, Michael Buesch <m@bues.ch>
 329 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 330   *
 331   * Licensed under the GNU/GPL. See COPYING for details.
 332   */
 333
 334  #include <linux/export.h>
 335 +#include <linux/platform_device.h>
 336  #include <linux/ssb/ssb.h>
 337  #include <linux/ssb/ssb_embedded.h>
 338  #include <linux/ssb/ssb_driver_pci.h>
 339 @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
 340  }
 341  EXPORT_SYMBOL(ssb_watchdog_timer_set);
 342
 343 +int ssb_watchdog_register(struct ssb_bus *bus)
 344 +{
 345 +       struct bcm47xx_wdt wdt = {};
 346 +       struct platform_device *pdev;
 347 +
 348 +       if (ssb_chipco_available(&bus->chipco)) {
 349 +               wdt.driver_data = &bus->chipco;
 350 +               wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
 351 +               wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
 352 +               wdt.max_timer_ms = bus->chipco.max_timer_ms;
 353 +       } else if (ssb_extif_available(&bus->extif)) {
 354 +               wdt.driver_data = &bus->extif;
 355 +               wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
 356 +               wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
 357 +               wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
 358 +       } else {
 359 +               return -ENODEV;
 360 +       }
 361 +
 362 +       pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
 363 +                                            bus->busnumber, &wdt,
 364 +                                            sizeof(wdt));
 365 +       if (IS_ERR(pdev)) {
 366 +               ssb_dprintk(KERN_INFO PFX
 367 +                           "can not register watchdog device, err: %li\n",
 368 +                           PTR_ERR(pdev));
 369 +               return PTR_ERR(pdev);
 370 +       }
 371 +
 372 +       bus->watchdog = pdev;
 373 +       return 0;
 374 +}
 375 +
 376  u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
 377  {
 378         unsigned long flags;
 379 --- a/drivers/ssb/main.c
 380 +++ b/drivers/ssb/main.c
 381 @@ -13,6 +13,7 @@
 382  #include <linux/delay.h>
 383  #include <linux/io.h>
 384  #include <linux/module.h>
 385 +#include <linux/platform_device.h>
 386  #include <linux/ssb/ssb.h>
 387  #include <linux/ssb/ssb_regs.h>
 388  #include <linux/ssb/ssb_driver_gige.h>
 389 @@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
 390                 if (sdev->dev)
 391                         device_unregister(sdev->dev);
 392         }
 393 +
 394 +#ifdef CONFIG_SSB_EMBEDDED
 395 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 396 +               platform_device_unregister(bus->watchdog);
 397 +#endif
 398  }
 399
 400  void ssb_bus_unregister(struct ssb_bus *bus)
 401 @@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
 402                 if (err)
 403                         goto error;
 404                 ssb_pcicore_init(&bus->pcicore);
 405 +               if (bus->bustype == SSB_BUSTYPE_SSB)
 406 +                       ssb_watchdog_register(bus);
 407                 ssb_bus_may_powerdown(bus);
 408
 409                 err = ssb_devices_register(bus);
 410 @@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
 411         case SSB_IDLOW_SSBREV_27:     /* same here */
 412                 return SSB_TMSLOW_REJECT;       /* this is a guess */
 413         default:
 414 -               printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
 415 -               WARN_ON(1);
 416 +               WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
 417         }
 418         return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
 419  }
 420 --- a/drivers/ssb/ssb_private.h
 421 +++ b/drivers/ssb/ssb_private.h
 422 @@ -3,6 +3,7 @@
 423
 424  #include <linux/ssb/ssb.h>
 425  #include <linux/types.h>
 426 +#include <linux/bcm47xx_wdt.h>
 427
 428
 429  #define PFX    "ssb: "
 430 @@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex
 431  /* driver_chipcommon_pmu.c */
 432  extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
 433  extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
 434 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
 435 +
 436 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
 437 +                                            u32 ticks);
 438 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
 439 +
 440 +#ifdef CONFIG_SSB_DRIVER_EXTIF
 441 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
 442 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
 443 +#else
 444 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
 445 +                                                  u32 ticks)
 446 +{
 447 +       return 0;
 448 +}
 449 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
 450 +                                                 u32 ms)
 451 +{
 452 +       return 0;
 453 +}
 454 +#endif
 455 +
 456 +#ifdef CONFIG_SSB_EMBEDDED
 457 +extern int ssb_watchdog_register(struct ssb_bus *bus);
 458 +#else /* CONFIG_SSB_EMBEDDED */
 459 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
 460 +{
 461 +       return 0;
 462 +}
 463 +#endif /* CONFIG_SSB_EMBEDDED */
 464
 465  #endif /* LINUX_SSB_PRIVATE_H_ */
 466 --- a/include/linux/ssb/ssb.h
 467 +++ b/include/linux/ssb/ssb.h
 468 @@ -8,6 +8,7 @@
 469  #include <linux/pci.h>
 470  #include <linux/mod_devicetable.h>
 471  #include <linux/dma-mapping.h>
 472 +#include <linux/platform_device.h>
 473
 474  #include <linux/ssb/ssb_regs.h>
 475
 476 @@ -432,6 +433,7 @@ struct ssb_bus {
 477  #ifdef CONFIG_SSB_EMBEDDED
 478         /* Lock for GPIO register access. */
 479         spinlock_t gpio_lock;
 480 +       struct platform_device *watchdog;
 481  #endif /* EMBEDDED */
 482
 483         /* Internal-only stuff follows. Do not touch. */
 484 --- a/include/linux/ssb/ssb_driver_chipcommon.h
 485 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
 486 @@ -504,7 +504,9 @@
 487  #define SSB_CHIPCO_FLASHCTL_ST_SE      0x02D8          /* Sector Erase */
 488  #define SSB_CHIPCO_FLASHCTL_ST_BE      0x00C7          /* Bulk Erase */
 489  #define SSB_CHIPCO_FLASHCTL_ST_DP      0x00B9          /* Deep Power-down */
 490 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG    0x03AB          /* Read Electronic Signature */
 491 +#define SSB_CHIPCO_FLASHCTL_ST_RES     0x03AB          /* Read Electronic Signature */
 492 +#define SSB_CHIPCO_FLASHCTL_ST_CSA     0x1000          /* Keep chip select asserted */
 493 +#define SSB_CHIPCO_FLASHCTL_ST_SSE     0x0220          /* Sub-sector Erase */
 494
 495  /* Status register bits for ST flashes */
 496  #define SSB_CHIPCO_FLASHSTA_ST_WIP     0x01            /* Write In Progress */
 497 @@ -589,6 +591,8 @@ struct ssb_chipcommon {
 498         /* Fast Powerup Delay constant */
 499         u16 fast_pwrup_delay;
 500         struct ssb_chipcommon_pmu pmu;
 501 +       u32 ticks_per_ms;
 502 +       u32 max_timer_ms;
 503  };
 504
 505  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
 506 @@ -628,8 +632,7 @@ enum ssb_clkmode {
 507  extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
 508                                      enum ssb_clkmode mode);
 509
 510 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
 511 -                                         u32 ticks);
 512 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
 513
 514  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
 515
 516 --- a/include/linux/ssb/ssb_driver_extif.h
 517 +++ b/include/linux/ssb/ssb_driver_extif.h
 518 @@ -152,6 +152,9 @@
 519  /* watchdog */
 520  #define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
 521
 522 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER   ((1 << 28) - 1)
 523 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS        (SSB_EXTIF_WATCHDOG_MAX_TIMER \
 524 +                                        / (SSB_EXTIF_WATCHDOG_CLK / 1000))
 525
 526
 527  #ifdef CONFIG_SSB_DRIVER_EXTIF
 528 @@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
 529  extern void ssb_extif_timing_init(struct ssb_extif *extif,
 530                                   unsigned long ns);
 531
 532 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 533 -                                        u32 ticks);
 534 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
 535
 536  /* Extif GPIO pin access */
 537  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
 538 @@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
 539  }
 540
 541  static inline
 542 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 543 -                                 u32 ticks)
 544 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
 545  {
 546  }
 547
 548 +static inline
 549 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 550 +{
 551 +       return 0;
 552 +}
 553 +
 554 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 555 +{
 556 +       return 0;
 557 +}
 558 +
 559 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
 560 +                                    u32 value)
 561 +{
 562 +       return 0;
 563 +}
 564 +
 565 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
 566 +                                      u32 value)
 567 +{
 568 +       return 0;
 569 +}
 570 +
 571 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
 572 +                                         u32 value)
 573 +{
 574 +       return 0;
 575 +}
 576 +
 577 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
 578 +                                        u32 value)
 579 +{
 580 +       return 0;
 581 +}
 582 +
 583 +#ifdef CONFIG_SSB_SERIAL
 584 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
 585 +                                       struct ssb_serial_port *ports)
 586 +{
 587 +       return 0;
 588 +}
 589 +#endif /* CONFIG_SSB_SERIAL */
 590 +
 591  #endif /* CONFIG_SSB_DRIVER_EXTIF */
 592  #endif /* LINUX_SSB_EXTIFCORE_H_ */
 593 --- a/include/linux/ssb/ssb_driver_mips.h
 594 +++ b/include/linux/ssb/ssb_driver_mips.h
 595 @@ -13,6 +13,12 @@ struct ssb_serial_port {
 596         unsigned int reg_shift;
 597  };
 598
 599 +struct ssb_pflash {
 600 +       bool present;
 601 +       u8 buswidth;
 602 +       u32 window;
 603 +       u32 window_size;
 604 +};
 605
 606  struct ssb_mipscore {
 607         struct ssb_device *dev;
 608 @@ -20,9 +26,7 @@ struct ssb_mipscore {
 609         int nr_serial_ports;
 610         struct ssb_serial_port serial_ports[4];
 611
 612 -       u8 flash_buswidth;
 613 -       u32 flash_window;
 614 -       u32 flash_window_size;
 615 +       struct ssb_pflash pflash;
 616  };
 617
 618  extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
 619 --- a/include/linux/ssb/ssb_regs.h
 620 +++ b/include/linux/ssb/ssb_regs.h
 621 @@ -485,7 +485,7 @@
 622  #define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
 623  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
 624  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
 625 -#define SSB_SPROM8_TEMPDELTA           0x00BA
 626 +#define SSB_SPROM8_TEMPDELTA           0x00BC
 627  #define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
 628  #define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
 629  #define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00