2 * BCM47XX support code for some chipcommon facilities (uart, jtagm)
4 * Copyright 2007, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
27 #define CC_ERROR(args)
30 #define CC_MSG(args) printf args
35 /* interested chipcommon interrupt source
42 #define MAX_CC_INT_SOURCE 5
44 /* chipc secondary isr info */
46 uint intmask; /* int mask */
47 cc_isr_fn isr; /* secondary isr handler */
48 void *cbdata; /* pointer to private data */
51 static cc_isr_info_t cc_isr_desc[MAX_CC_INT_SOURCE];
53 /* chip common intmask */
54 static uint32 cc_intmask = 0;
56 static bool BCMINITFN(serial_exists) (osl_t * osh, uint8 * regs) {
57 uint8 save_mcr, status1;
59 save_mcr = R_REG(osh, ®s[UART_MCR]);
60 W_REG(osh, ®s[UART_MCR], UART_MCR_LOOP | 0x0a);
61 status1 = R_REG(osh, ®s[UART_MSR]) & 0xf0;
62 W_REG(osh, ®s[UART_MCR], save_mcr);
64 return (status1 == 0x90);
67 static void __init sb_extif_serial_init(sb_t * sbh, void *regs,
68 sb_serial_init_fn add)
70 osl_t *osh = sb_osh(sbh);
71 extifregs_t *eir = (extifregs_t *) regs;
77 /* Determine external UART register base */
78 sb = (sbconfig_t *) ((ulong) eir + SBCONFIGOFF);
79 base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
84 /* Disable GPIO interrupt initially */
85 W_REG(osh, &eir->gpiointpolarity, 0);
86 W_REG(osh, &eir->gpiointmask, 0);
88 /* Search for external UARTs */
90 for (i = 0; i < 2; i++) {
91 regs = (void *)REG_MAP(base + (i * 8), 8);
92 if (serial_exists(osh, regs)) {
93 /* Set GPIO 1 to be the external UART IRQ */
94 W_REG(osh, &eir->gpiointmask, 2);
95 /* XXXDetermine external UART clock */
97 add(regs, irq, 13500000, 0);
101 /* Add internal UART if enabled */
102 if (R_REG(osh, &eir->corecontrol) & CC_UE)
104 add((void *)&eir->uartdata, irq, sb_clock(sbh), 2);
108 * Initializes UART access. The callback function will be called once
111 void BCMINITFN(sb_serial_init) (sb_t * sbh, sb_serial_init_fn add) {
115 uint32 rev, cap, pll, baud_base, div;
121 regs = sb_setcore(sbh, SB_EXTIF, 0);
123 sb_extif_serial_init(sbh, regs, add);
127 cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0);
130 /* Determine core revision and capabilities */
133 pll = cap & CC_CAP_PLL_MASK;
138 if (pll == PLL_TYPE1) {
140 baud_base = sb_clock_rate(pll,
141 R_REG(osh, &cc->clockcontrol_n),
142 R_REG(osh, &cc->clockcontrol_m2));
145 /* 5354 chip common uart uses a constant clock
146 * frequency of 25MHz */
147 if (sb_corerev(sbh) == 20) {
148 /* Set the override bit so we don't divide it */
149 W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
150 baud_base = 25000000;
151 } else if (rev >= 11 && rev != 15) {
152 /* Fixed ALP clock */
153 baud_base = sb_alp_clock(sbh);
155 /* Turn off UART clock before switching clock source */
157 AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
158 /* Set the override bit so we don't divide it */
159 OR_REG(osh, &cc->corecontrol, CC_UARTCLKO);
161 OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
162 } else if (rev >= 3) {
163 /* Internal backplane clock */
164 baud_base = sb_clock(sbh);
165 div = 2; /* Minimum divisor */
166 W_REG(osh, &cc->clkdiv,
167 ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
169 /* Fixed internal backplane clock */
170 baud_base = 88000000;
174 /* Clock source depends on strapping if UartClkOverride is unset */
176 && ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
177 if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) {
178 /* Internal divided backplane clock */
181 /* Assume external clock of 1.8432 MHz */
187 /* Add internal UARTs */
188 n = cap & CC_CAP_UARTS_MASK;
189 for (i = 0; i < n; i++) {
190 /* Register offset changed after revision 0 */
192 regs = (void *)((ulong) & cc->uart0data + (i * 256));
194 regs = (void *)((ulong) & cc->uart0data + (i * 8));
197 add(regs, irq, baud_base, 0);
203 * Initialize jtag master and return handle for
204 * jtag_rwreg. Returns NULL on failure.
206 void *sb_jtagm_init(sb_t * sbh, uint clkd, bool exttap)
210 if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
211 chipcregs_t *cc = (chipcregs_t *) regs;
215 * Determine jtagm availability from
216 * core revision and capabilities.
220 * Corerev 10 has jtagm, but the only chip
221 * with it does not have a mips, and
222 * the layout of the jtagcmd register is
223 * different. We'll only accept >= 11.
228 if ((sbh->cccaps & CC_CAP_JTAGP) == 0)
231 /* Set clock divider if requested */
233 tmp = R_REG(osh, &cc->clkdiv);
235 (tmp & ~CLKD_JTAG) | ((clkd << CLKD_JTAG_SHIFT) &
237 W_REG(osh, &cc->clkdiv, tmp);
241 tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
242 W_REG(osh, &cc->jtagctrl, tmp);
248 void sb_jtagm_disable(osl_t * osh, void *h)
250 chipcregs_t *cc = (chipcregs_t *) h;
252 W_REG(osh, &cc->jtagctrl, R_REG(osh, &cc->jtagctrl) & ~JCTRL_EN);
256 * Read/write a jtag register. Assumes a target with
257 * 8 bit IR and 32 bit DR.
259 #define IRWIDTH 8 /* Default Instruction Register width */
260 #define DRWIDTH 32 /* Default Data Register width */
262 uint32 jtag_rwreg(osl_t * osh, void *h, uint32 ir, uint32 dr)
264 chipcregs_t *cc = (chipcregs_t *) h;
267 W_REG(osh, &cc->jtagir, ir);
268 W_REG(osh, &cc->jtagdr, dr);
269 tmp = JCMD_START | JCMD_ACC_IRDR |
270 ((IRWIDTH - 1) << JCMD_IRW_SHIFT) | (DRWIDTH - 1);
271 W_REG(osh, &cc->jtagcmd, tmp);
272 while (((tmp = R_REG(osh, &cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
276 tmp = R_REG(osh, &cc->jtagdr);
282 * Interface to register chipc secondary isr
285 BCMINITFN(sb_cc_register_isr) (sb_t * sbh, cc_isr_fn isr, uint32 ccintmask,
292 /* Save the current core index */
293 origidx = sb_coreidx(sbh);
294 regs = sb_setcore(sbh, SB_CC, 0);
297 for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
298 if (cc_isr_desc[i].isr == NULL) {
299 cc_isr_desc[i].isr = isr;
300 cc_isr_desc[i].cbdata = cbdata;
301 cc_isr_desc[i].intmask = ccintmask;
308 cc_intmask = R_REG(sb_osh(sbh), ®s->intmask);
309 cc_intmask |= ccintmask;
310 W_REG(sb_osh(sbh), ®s->intmask, cc_intmask);
313 /* restore original coreidx */
314 sb_setcoreidx(sbh, origidx);
319 * chipc primary interrupt handler
321 void sb_cc_isr(sb_t * sbh, chipcregs_t * regs)
327 /* prior to rev 21 chipc interrupt means uart and gpio */
328 if (sbh->ccrev >= 21)
329 ccintstatus = R_REG(sb_osh(sbh), ®s->intstatus) & cc_intmask;
331 ccintstatus = (CI_UART | CI_GPIO);
333 for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
334 if ((cc_isr_desc[i].isr != NULL) &&
335 (intstatus = (cc_isr_desc[i].intmask & ccintstatus))) {
336 (cc_isr_desc[i].isr) (cc_isr_desc[i].cbdata, intstatus);