1 --- a/drivers/mtd/spi-nor/spi-nor.c
2 +++ b/drivers/mtd/spi-nor/spi-nor.c
3 @@ -565,14 +565,14 @@ static const struct spi_device_id spi_no
4 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
7 - { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
8 - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
9 - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
10 - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
11 - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
12 - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
13 - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
14 - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
15 + { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
16 + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) },
17 + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
18 + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
19 + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
20 + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
21 + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
22 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
25 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
26 @@ -896,6 +896,45 @@ static int spansion_quad_enable(struct s
30 +static int micron_quad_enable(struct spi_nor *nor)
35 + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
37 + dev_err(nor->dev, "error %d reading EVCR\n", ret);
43 + /* set EVCR, enable quad I/O */
44 + nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
45 + ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
47 + dev_err(nor->dev, "error while writing EVCR register\n");
51 + ret = spi_nor_wait_till_ready(nor);
55 + /* read EVCR and check it */
56 + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
58 + dev_err(nor->dev, "error %d reading EVCR\n", ret);
61 + if (val & EVCR_QUAD_EN_MICRON) {
62 + dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
69 static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
72 @@ -908,6 +947,13 @@ static int set_quad_mode(struct spi_nor
77 + status = micron_quad_enable(nor);
79 + dev_err(nor->dev, "Micron quad-read not enabled\n");
84 status = spansion_quad_enable(nor);
86 --- a/include/linux/mtd/spi-nor.h
87 +++ b/include/linux/mtd/spi-nor.h
89 /* Used for Spansion flashes only. */
90 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
92 +/* Used for Micron flashes only. */
93 +#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
94 +#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
96 /* Status Register bits. */
97 #define SR_WIP 1 /* Write in progress */
98 #define SR_WEL 2 /* Write enable latch */
101 #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
103 +/* Enhanced Volatile Configuration Register bits */
104 +#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
106 /* Flag Status Register bits */
107 #define FSR_READY 0x80