target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define PLL_SEC_CONFIG          0x18050004
  17 #define PLL_ETH0_INT_CLOCK      0x18050010
  18 #define PLL_ETH1_INT_CLOCK      0x18050014
  19 #define PLL_ETH_EXT_CLOCK       0x18050018
  20
  21 #define ag71xx_pll_shift(_ag)   (((_ag)->pdev->id) ? 19 : 17)
  22 #define ag71xx_pll_offset(_ag)  (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
  23                                                    : PLL_ETH0_INT_CLOCK)
  24
  25 static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
  26 {
  27         void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4);
  28         void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
  29         u32 s;
  30         u32 t;
  31
  32         s = ag71xx_pll_shift(ag);
  33
  34         t = __raw_readl(pll_cfg);
  35         t &= ~(3 << s);
  36         t |=  (2 << s);
  37         __raw_writel(t, pll_cfg);
  38         udelay(100);
  39
  40         __raw_writel(pll_val, pll_reg);
  41
  42         t |= (3 << s);
  43         __raw_writel(t, pll_cfg);
  44         udelay(100);
  45
  46         t &= ~(3 << s);
  47         __raw_writel(t, pll_cfg);
  48         udelay(100);
  49         DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
  50                         (unsigned int)pll_reg, __raw_readl(pll_reg));
  51
  52         iounmap(pll_cfg);
  53         iounmap(pll_reg);
  54 }
  55
  56 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
  57 {
  58         switch (ag->speed) {
  59         case SPEED_1000:
  60                 return "1000";
  61         case SPEED_100:
  62                 return "100";
  63         case SPEED_10:
  64                 return "10";
  65         }
  66
  67         return "?";
  68 }
  69
  70 #if 1
  71 #define PLL_VAL_1000    0x00110000
  72 #define PLL_VAL_100     0x00001099
  73 #define PLL_VAL_10      0x00991099
  74 #else
  75 #define PLL_VAL_1000    0x01111000
  76 #define PLL_VAL_100     0x09991000
  77 #define PLL_VAL_10      0x09991999
  78 #endif
  79
  80 static void ag71xx_phy_link_update(struct ag71xx *ag)
  81 {
  82         u32 cfg2;
  83         u32 ifctl;
  84         u32 pll;
  85         u32 fifo5;
  86         u32 mii_speed;
  87
  88         if (!ag->link) {
  89                 netif_carrier_off(ag->dev);
  90                 printk(KERN_INFO "%s: link down\n", ag->dev->name);
  91                 return;
  92         }
  93
  94         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
  95         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
  96         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
  97
  98         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
  99         ifctl &= ~(MAC_IFCTL_SPEED);
 100
 101         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 102         fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK;
 103
 104         switch (ag->speed) {
 105         case SPEED_1000:
 106                 mii_speed =  MII_CTRL_SPEED_1000;
 107                 cfg2 |= MAC_CFG2_IF_1000;
 108                 pll = PLL_VAL_1000;
 109                 fifo5 |= FIFO_CFG5_BYTE_PER_CLK;
 110                 break;
 111         case SPEED_100:
 112                 mii_speed = MII_CTRL_SPEED_100;
 113                 cfg2 |= MAC_CFG2_IF_10_100;
 114                 ifctl |= MAC_IFCTL_SPEED;
 115                 pll = PLL_VAL_100;
 116                 break;
 117         case SPEED_10:
 118                 mii_speed = MII_CTRL_SPEED_10;
 119                 cfg2 |= MAC_CFG2_IF_10_100;
 120                 pll = PLL_VAL_10;
 121                 break;
 122         default:
 123                 BUG();
 124                 return;
 125         }
 126
 127         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
 128         ag71xx_set_pll(ag, pll);
 129         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
 130
 131         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 132         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 133         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 134
 135         netif_carrier_on(ag->dev);
 136         printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
 137                 ag->dev->name,
 138                 ag71xx_speed_str(ag),
 139                 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 140
 141         DBG("%s: fifo1=%#x, fifo2=%#x, fifo3=%#x, fifo4=%#x, fifo5=%#x\n",
 142                 ag->dev->name,
 143                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
 144                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2),
 145                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
 146                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
 147                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
 148
 149         DBG("%s: mac_cfg2=%#x, ifctl=%#x, mii_ctrl=%#x\n",
 150                 ag->dev->name,
 151                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
 152                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
 153                 ag71xx_mii_ctrl_rr(ag));
 154 }
 155
 156 static void ag71xx_phy_link_adjust(struct net_device *dev)
 157 {
 158         struct ag71xx *ag = netdev_priv(dev);
 159         struct phy_device *phydev = ag->phy_dev;
 160         unsigned long flags;
 161         int status_change = 0;
 162
 163         spin_lock_irqsave(&ag->lock, flags);
 164
 165         if (phydev->link) {
 166                 if (ag->duplex != phydev->duplex
 167                     || ag->speed != phydev->speed) {
 168                         status_change = 1;
 169                 }
 170         }
 171
 172         if (phydev->link != ag->link) {
 173                 if (phydev->link)
 174                         netif_schedule(dev);
 175
 176                 status_change = 1;
 177         }
 178
 179         ag->link = phydev->link;
 180         ag->duplex = phydev->duplex;
 181         ag->speed = phydev->speed;
 182
 183         if (status_change)
 184                 ag71xx_phy_link_update(ag);
 185
 186         spin_unlock_irqrestore(&ag->lock, flags);
 187 }
 188
 189 void ag71xx_phy_start(struct ag71xx *ag)
 190 {
 191         if (ag->phy_dev) {
 192                 phy_start(ag->phy_dev);
 193         } else {
 194                 ag->duplex = DUPLEX_FULL;
 195                 ag->speed = SPEED_100;
 196                 ag->link = 1;
 197                 ag71xx_phy_link_update(ag);
 198         }
 199 }
 200
 201 void ag71xx_phy_stop(struct ag71xx *ag)
 202 {
 203         if (ag->phy_dev) {
 204                 phy_stop(ag->phy_dev);
 205         } else {
 206                 ag->duplex = -1;
 207                 ag->link = 0;
 208                 ag->speed = 0;
 209                 ag71xx_phy_link_update(ag);
 210         }
 211 }
 212
 213 int ag71xx_phy_connect(struct ag71xx *ag)
 214 {
 215         struct net_device *dev = ag->dev;
 216         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 217         struct phy_device *phydev = NULL;
 218         int phy_count = 0;
 219         int phy_addr;
 220
 221         if (ag->mii_bus) {
 222                 /* TODO: use mutex of the mdio bus */
 223                 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 224                         if (!(pdata->phy_mask & (1 << phy_addr)))
 225                                 continue;
 226
 227                         if (ag->mii_bus->phy_map[phy_addr] == NULL)
 228                                 continue;
 229
 230                         DBG("%s: PHY found at %s, uid=%08x\n",
 231                                 dev->name,
 232                                 ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
 233                                 ag->mii_bus->phy_map[phy_addr]->phy_id);
 234
 235                         if (phydev == NULL)
 236                                 phydev = ag->mii_bus->phy_map[phy_addr];
 237
 238                         phy_count++;
 239                 }
 240         }
 241
 242         switch (phy_count) {
 243         case 0:
 244                 printk(KERN_ERR "%s: no PHY found\n", dev->name);
 245                 return -ENODEV;
 246         case 1:
 247                 ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
 248                         &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
 249
 250                 if (IS_ERR(ag->phy_dev)) {
 251                         printk(KERN_ERR "%s: could not connect to PHY at %s\n",
 252                                 dev->name, phydev->dev.bus_id);
 253                         return PTR_ERR(ag->phy_dev);
 254                 }
 255
 256                 /* mask with MAC supported features */
 257                 phydev->supported &= (SUPPORTED_10baseT_Half
 258                         | SUPPORTED_10baseT_Full
 259                         | SUPPORTED_100baseT_Half
 260                         | SUPPORTED_100baseT_Full
 261                         | SUPPORTED_Autoneg
 262                         | SUPPORTED_MII
 263                         | SUPPORTED_TP);
 264
 265                 phydev->advertising = phydev->supported;
 266
 267                 printk(KERN_DEBUG "%s: connected to PHY at %s "
 268                         "[uid=%08x, driver=%s]\n",
 269                         dev->name, phydev->dev.bus_id,
 270                         phydev->phy_id, phydev->drv->name);
 271
 272                 ag->link = 0;
 273                 ag->speed = 0;
 274                 ag->duplex = -1;
 275                 break;
 276         default:
 277                 ag->phy_dev = NULL;
 278                 printk(KERN_DEBUG "%s: connected to multiple PHYs (%d)\n",
 279                         dev->name, phy_count);
 280                 break;
 281         }
 282
 283         return 0;
 284 }
 285
 286 void ag71xx_phy_disconnect(struct ag71xx *ag)
 287 {
 288         if (ag->phy_dev)
 289                 phy_disconnect(ag->phy_dev);
 290 }