target/linux/ar7/files/include/asm-mips/ar7/titan.h

   1 /*
   2  * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18 #ifndef __AR7_TITAN_H__
  19 #define __AR7_TITAN_H__
  20
  21 #ifndef __AR7_GPIO_H__
  22 #include <asm/ar7/gpio.h>
  23 #endif
  24
  25 typedef enum TITAN_GPIO_PIN_MODE_tag
  26 {
  27     FUNCTIONAL_PIN = 0,
  28     GPIO_PIN = 1
  29 } TITAN_GPIO_PIN_MODE_T;
  30
  31 typedef enum TITAN_GPIO_PIN_DIRECTION_tag
  32 {
  33     GPIO_OUTPUT_PIN = 0,
  34     GPIO_INPUT_PIN = 1
  35 } TITAN_GPIO_PIN_DIRECTION_T;
  36
  37 /**********************************************************************
  38  *  GPIO Control
  39  **********************************************************************/
  40
  41 typedef struct
  42 {
  43     int pinSelReg;
  44     int shift;
  45     int func;
  46
  47 } GPIO_CFG;
  48
  49 static GPIO_CFG gptable[]= {
  50                       /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
  51                       {4,24,1},
  52                       {4,26,1},
  53                       {4,28,1},
  54                       {4,30,1},
  55                       {5,6,1},
  56                       {5,8,1},
  57                       {5,10,1},
  58                       {5,12,1},
  59                       {7,14,3},
  60                       {7,16,3},
  61                       {7,18,3},
  62                       {7,20,3},
  63                       {7,22,3},
  64                       {7,26,3},
  65                       {7,28,3},
  66                       {7,30,3},
  67                       {8,0,3},
  68                       {8,2,3},
  69                       {8,4,3},
  70                       {8,10,3},
  71                       {8,14,3},
  72                       {8,16,3},
  73                       {8,18,3},
  74                       {8,20,3},
  75                       {9,8,3},
  76                       {9,10,3},
  77                       {9,12,3},
  78                       {9,14,3},
  79                       {9,18,3},
  80                       {9,20,3},
  81                       {9,24,3},
  82                       {9,26,3},
  83                       {9,28,3},
  84                       {9,30,3},
  85                       {10,0,3},
  86                       {10,2,3},
  87                       {10,8,3},
  88                       {10,10,3},
  89                       {10,12,3},
  90                       {10,14,3},
  91                       {13,12,3},
  92                       {13,14,3},
  93                       {13,16,3},
  94                       {13,18,3},
  95                       {13,24,3},
  96                       {13,26,3},
  97                       {13,28,3},
  98                       {13,30,3},
  99                       {14,2,3},
 100                       {14,6,3},
 101                       {14,8,3},
 102                       {14,12,3}
 103 };
 104
 105 typedef struct
 106 {
 107     volatile unsigned int reg[21];
 108 }
 109 PIN_SEL_REG_ARRAY_T;
 110
 111 typedef struct
 112 {
 113     unsigned int data_in [2];
 114     unsigned int data_out[2];
 115     unsigned int dir[2];
 116     unsigned int enable[2];
 117
 118 } TITAN_GPIO_CONTROL_T;
 119
 120 #define AVALANCHE_PIN_SEL_BASE        0xA861160C /*replace with KSEG1ADDR()*/
 121
 122 static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
 123                         TITAN_GPIO_PIN_DIRECTION_T pin_direction)
 124 {
 125     int reg_index = 0;
 126     int mux_status;
 127     GPIO_CFG  gpio_cfg;
 128     volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
 129     volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 130
 131     if (gpio_pin > 51 )
 132         return(-1);
 133
 134     gpio_cfg = gptable[gpio_pin];
 135     mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
 136     if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
 137     {
 138         return(-1); /* Pin have been configured for non GPIO funcs. */
 139     }
 140
 141     /* Set the pin to be used as GPIO. */
 142     pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
 143
 144     /* Check whether gpio refers to the first GPIO reg or second. */
 145     if(gpio_pin > 31)
 146     {
 147         reg_index = 1;
 148         gpio_pin -= 32;
 149     }
 150
 151     if(pin_mode)
 152         gpio_cntl->enable[reg_index] |=  (1 << gpio_pin); /* Enable */
 153     else
 154         gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
 155
 156     if(pin_direction)
 157         gpio_cntl->dir[reg_index] |=  (1 << gpio_pin); /* Input */
 158     else
 159         gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
 160
 161     return(0);
 162
 163 }/* end of function titan_gpio_ctrl */
 164
 165 static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
 166 {
 167     volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 168
 169     if(reg_index > 1)
 170        return (-1);
 171
 172     *in_val = gpio_cntl->data_in[reg_index];
 173
 174     return (0);
 175 }
 176
 177
 178 #endif