2 * ########################################################################
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4 * This program is free software; you can distribute it and/or modify it
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5 * under the terms of the GNU General Public License (Version 2) as
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6 * published by the Free Software Foundation.
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8 * This program is distributed in the hope it will be useful, but WITHOUT
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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13 * You should have received a copy of the GNU General Public License along
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14 * with this program; if not, write to the Free Software Foundation, Inc.,
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15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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17 * ########################################################################
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22 * device driver of clock generation unit of Danube chip
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27 * History & Modification Tag:
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28 * ___________________________________________________________________________
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29 * | Tag | Comments | Modifier & Time |
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30 * |--------+---------------------------------------------+------------------|
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31 * | S0.0 | First version of this driver and the tag is | Samuels Xu Liang |
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32 * | | implied. | 19 Jul 2005 |
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33 * ---------------------------------------------------------------------------
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39 * ####################################
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41 * ####################################
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47 #include <linux/config.h>
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48 #include <linux/kernel.h>
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49 #include <linux/module.h>
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50 #include <linux/version.h>
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51 #include <linux/types.h>
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52 #include <linux/fs.h>
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53 #include <linux/miscdevice.h>
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54 #include <linux/init.h>
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55 #include <asm/uaccess.h>
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56 #include <asm/unistd.h>
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57 #include <asm/irq.h>
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58 #include <linux/errno.h>
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61 * Chip Specific Head File
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63 #include "ifx_cgu.h"
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67 * ####################################
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69 * ####################################
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72 #define DEBUG_ON_AMAZON 1
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73 #define DEBUG_PRINT_INFO 1
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76 * Frequency of Clock Direct Feed from The Analog Line Driver Chip
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78 #define BASIC_INPUT_CLOCK_FREQUENCY 35328000
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83 #define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
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84 #define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
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87 * CGU Register Mapping
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89 #define DANUBE_CGU (KSEG1 + 0x1F103000)
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90 #define DANUBE_CGU_DIV ((volatile u32*)(DANUBE_CGU + 0x0000))
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91 #define DANUBE_CGU_PLL_NMK0 ((volatile u32*)(DANUBE_CGU + 0x0004))
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92 #define DANUBE_CGU_PLL_SR0 ((volatile u32*)(DANUBE_CGU + 0x0008))
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93 #define DANUBE_CGU_PLL_NMK1 ((volatile u32*)(DANUBE_CGU + 0x000C))
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94 #define DANUBE_CGU_PLL_SR1 ((volatile u32*)(DANUBE_CGU + 0x0010))
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95 #define DANUBE_CGU_PLL_SR2 ((volatile u32*)(DANUBE_CGU + 0x0014))
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96 #define DANUBE_CGU_IF_CLK ((volatile u32*)(DANUBE_CGU + 0x0018))
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97 #define DANUBE_CGU_OSC_CTRL ((volatile u32*)(DANUBE_CGU + 0x001C))
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98 #define DANUBE_CGU_SMD ((volatile u32*)(DANUBE_CGU + 0x0020))
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99 #define DANUBE_CGU_CRD ((volatile u32*)(DANUBE_CGU + 0x0024))
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100 #define DANUBE_CGU_CT1SR ((volatile u32*)(DANUBE_CGU + 0x0028))
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101 #define DANUBE_CGU_CT2SR ((volatile u32*)(DANUBE_CGU + 0x002C))
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102 #define DANUBE_CGU_PCMCR ((volatile u32*)(DANUBE_CGU + 0x0030))
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103 #define DANUBE_CGU_MUX ((volatile u32*)(DANUBE_CGU + 0x0034))
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106 * CGU Divider Register
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108 #define CGU_DIV_SFTR (*DANUBE_CGU_DIV & (1 << 31))
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109 #define CGU_DIV_DIVE (*DANUBE_CGU_DIV & (1 << 16))
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110 #define CGU_DIV_IOR GET_BITS(*DANUBE_CGU_DIV, 5, 4)
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111 #define CGU_DIV_FKS GET_BITS(*DANUBE_CGU_DIV, 3, 2)
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112 #define CGU_DIV_FBS GET_BITS(*DANUBE_CGU_DIV, 1, 0)
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115 * CGU PLL0 NMK Register
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117 #define CGU_PLL_NMK0_PLLN ((*DANUBE_CGU_PLL_NMK0 & (0xFFFFFFFF ^ ((1 << 24) - 1))) >> 24)
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118 #define CGU_PLL_NMK0_PLLM GET_BITS(*DANUBE_CGU_PLL_NMK0, 23, 20)
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119 #define CGU_PLL_NMK0_PLLK GET_BITS(*DANUBE_CGU_PLL_NMK0, 19, 0)
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122 * CGU PLL0 Status Register
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124 #define CGU_PLL_SR0_PLLDIV ((*DANUBE_CGU_PLL_SR0 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)
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125 #define CGU_PLL_SR0_PLLDEN (*DANUBE_CGU_PLL_SR0 & (1 << 26))
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126 #define CGU_PLL_SR0_PLLPSE GET_BITS(*DANUBE_CGU_PLL_SR0, 5, 4)
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127 #define CGU_PLL_SR0_PLLB (*DANUBE_CGU_PLL_SR0 & (1 << 2))
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128 #define CGU_PLL_SR0_PLLL (*DANUBE_CGU_PLL_SR0 & (1 << 1))
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129 #define CGU_PLL_SR0_PLLEN (*DANUBE_CGU_PLL_SR0 & (1 << 0))
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131 #define CGU_PLL_SR0_DSMSEL 1
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132 #define CGU_PLL_SR0_PHASE_DIV_EN 1
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135 * CGU PLL1 NMK Register
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137 #define CGU_PLL_NMK1_PLLN ((*DANUBE_CGU_PLL_NMK1 & (0xFFFFFFFF ^ ((1 << 24) - 1))) >> 24)
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138 #define CGU_PLL_NMK1_PLLM GET_BITS(*DANUBE_CGU_PLL_NMK1, 23, 20)
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139 #define CGU_PLL_NMK1_PLLK GET_BITS(*DANUBE_CGU_PLL_NMK1, 19, 0)
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142 * CGU PLL1 Status Register
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144 #define CGU_PLL_SR1_PLLDIV ((*DANUBE_CGU_PLL_SR1 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)
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145 #define CGU_PLL_SR1_PLLDEN (*DANUBE_CGU_PLL_SR1 & (1 << 26))
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146 #define CGU_PLL_SR1_PLLPSE GET_BITS(*DANUBE_CGU_PLL_SR1, 5, 4)
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147 #define CGU_PLL_SR1_PLLB (*DANUBE_CGU_PLL_SR1 & (1 << 2))
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148 #define CGU_PLL_SR1_PLLL (*DANUBE_CGU_PLL_SR1 & (1 << 1))
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149 #define CGU_PLL_SR1_PLLEN (*DANUBE_CGU_PLL_SR1 & (1 << 0))
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151 #define CGU_PLL_SR1_DSMSEL 1
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152 #define CGU_PLL_SR1_PHASE_DIV_EN 1
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155 * CGU PLL2 Status Register
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157 #define CGU_PLL_SR2_PLLDIV ((*DANUBE_CGU_PLL_SR2 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)
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158 #define CGU_PLL_SR2_PLLDEN (*DANUBE_CGU_PLL_SR2 & (1 << 27))
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159 #define CGU_PLL_SR2_PLLN GET_BITS(*DANUBE_CGU_PLL_SR2, 25, 20)
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160 #define CGU_PLL_SR2_PLLM GET_BITS(*DANUBE_CGU_PLL_SR2, 19, 16)
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161 #define CGU_PLL_SR2_PLLPS (*DANUBE_CGU_PLL_SR2 & (1 << 5))
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162 #define CGU_PLL_SR2_PLLPE (*DANUBE_CGU_PLL_SR2 & (1 << 4))
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163 #define CGU_PLL_SR2_PLLB (*DANUBE_CGU_PLL_SR2 & (1 << 2))
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164 #define CGU_PLL_SR2_PLLL (*DANUBE_CGU_PLL_SR2 & (1 << 1))
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165 #define CGU_PLL_SR2_PLLEN (*DANUBE_CGU_PLL_SR2 & (1 << 0))
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168 * CGU Interface Clock Register
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170 #define CGU_IF_CLK_CLKOD0 GET_BITS(*DANUBE_CGU_IF_CLK, 27, 26)
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171 #define CGU_IF_CLK_CLKOD1 GET_BITS(*DANUBE_CGU_IF_CLK, 25, 24)
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172 #define CGU_IF_CLK_CLKOD2 GET_BITS(*DANUBE_CGU_IF_CLK, 23, 22)
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173 #define CGU_IF_CLK_CLKOD3 GET_BITS(*DANUBE_CGU_IF_CLK, 21, 20)
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174 #define CGU_IF_CLK_PDA (*DANUBE_CGU_IF_CLK & (1 << 18))
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175 #define CGU_IF_CLK_PCI_B (*DANUBE_CGU_IF_CLK & (1 << 17))
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176 #define CGU_IF_CLK_PCIBM (*DANUBE_CGU_IF_CLK & (1 << 16))
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177 #define CGU_IF_CLK_MIICS (*DANUBE_CGU_IF_CLK & (1 << 3))
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178 #define CGU_IF_CLK_USBCS (*DANUBE_CGU_IF_CLK & (1 << 2))
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179 #define CGU_IF_CLK_PCIF (*DANUBE_CGU_IF_CLK & (1 << 1))
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180 #define CGU_IF_CLK_PCIS (*DANUBE_CGU_IF_CLK & (1 << 0))
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183 * CGU Oscillator Control Register
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185 #define CGU_OSC_CTRL GET_BITS(*DANUBE_CGU_OSC_CTRL, 1, 0)
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188 * CGU SDRAM Memory Delay Register
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190 #define CGU_SMD_CLKI (*DANUBE_CGU_SMD & (1 << 31))
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191 #define CGU_SMD_MIDS GET_BITS(*DANUBE_CGU_SMD, 17, 12)
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192 #define CGU_SMD_MODS GET_BITS(*DANUBE_CGU_SMD, 11, 6)
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193 #define CGU_SMD_MDSEL GET_BITS(*DANUBE_CGU_SMD, 5, 0)
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196 * CGU CPU Clock Reduction Register
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198 #define CGU_CRD_SFTR (*DANUBE_CGU_CRD & (1 << 31))
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199 #define CGU_CRD_DIVE (*DANUBE_CGU_CRD & (1 << 16))
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200 #define CGU_CRD_CRD1 GET_BITS(*DANUBE_CGU_CRD, 3, 2)
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201 #define CGU_CRD_CRD GET_BITS(*DANUBE_CGU_CRD, 1, 0)
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204 * CGU CT Status Register 1
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206 #define CGU_CT1SR_PDOUT GET_BITS(*DANUBE_CGU_CT1SR, 13, 0)
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209 * CGU CT Status Register 2
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211 #define CGU_CT2SR_PLL1K GET_BITS(*DANUBE_CGU_CT2SR, 9, 0)
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214 * CGU PCM Control Register
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216 #define CGU_PCMCR_DCL1 GET_BITS(*DANUBE_CGU_PCMCR, 27, 25)
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217 #define CGU_PCMCR_MUXDCL (*DANUBE_CGU_PCMCR & (1 << 22))
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218 #define CGU_PCMCR_MUXFSC (*DANUBE_CGU_PCMCR & (1 << 18))
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219 #define CGU_PCMCR_PCM_SL (*DANUBE_CGU_PCMCR & (1 << 13))
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220 #define CGU_PCMCR_DNTR (*DANUBE_CGU_PCMCR & (1 << 12))
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223 * CGU Clock Mux Register
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225 #define CGU_MUX_MII_CLK (*DANUBE_CGU_MUX & (1 << 6))
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226 #define CGU_MUX_SUB_SYS GET_BITS(*DANUBE_CGU_MUX, 5, 3)
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227 #define CGU_MUX_PP32 GET_BITS(*DANUBE_CGU_MUX, 1, 0)
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231 * ####################################
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232 * Preparation of Debug on Amazon Chip
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233 * ####################################
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237 * If try module on Amazon chip, prepare some tricks to prevent invalid memory write.
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239 #if defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
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240 u32 g_pFakeRegisters[0x0100];
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243 #define DANUBE_CGU ((u32)g_pFakeRegisters)
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244 #endif // defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
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248 * ####################################
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250 * ####################################
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255 * ####################################
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257 * ####################################
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261 * Pre-declaration of File Operations
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263 static ssize_t cgu_read(struct file *, char *, size_t, loff_t *);
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264 static ssize_t cgu_write(struct file *, const char *, size_t, loff_t *);
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265 static int cgu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
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266 static int cgu_open(struct inode *, struct file *);
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267 static int cgu_release(struct inode *, struct file *);
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270 * Pre-declaration of 64-bit Unsigned Integer Operation
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272 static inline void uint64_multiply(unsigned int, unsigned int, unsigned int *);
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273 static inline void uint64_divide(unsigned int *, unsigned int, unsigned int *, unsigned int *);
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276 * Calculate PLL Frequency
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278 static inline u32 cal_dsm(u32, u32);
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279 static inline u32 mash_dsm(u32, u32, u32);
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280 static inline u32 ssff_dsm_1(u32, u32, u32);
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281 static inline u32 ssff_dsm_2(u32, u32, u32);
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282 static inline u32 dsm(u32 M, u32, u32, int, int);
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283 static inline u32 cgu_get_pll0_fosc(void);
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284 static inline u32 cgu_get_pll0_fps(void);
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285 static inline u32 cgu_get_pll0_fdiv(void);
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286 static inline u32 cgu_get_pll1_fosc(void);
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287 static inline u32 cgu_get_pll1_fps(void);
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288 static inline u32 cgu_get_pll1_fdiv(void);
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289 static inline u32 cgu_get_pll2_fosc(void);
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290 static inline u32 cgu_get_pll2_fps(void);
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295 u32 cgu_get_mips_clock(int);
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296 u32 cgu_get_cpu_clock(void);
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297 u32 cgu_get_io_region_clock(void);
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298 u32 cgu_get_fpi_bus_clock(int);
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299 u32 cgu_get_pp32_clock(void);
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300 u32 cgu_get_pci_clock(void);
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301 u32 cgu_get_ethernet_clock(void);
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302 u32 cgu_get_usb_clock(void);
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303 u32 cgu_get_clockout(int);
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307 * ####################################
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309 * ####################################
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312 static struct file_operations cgu_fops = {
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313 owner: THIS_MODULE,
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319 release: cgu_release
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322 static struct miscdevice cgu_miscdev = {
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323 MISC_DYNAMIC_MINOR,
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330 * ####################################
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332 * ####################################
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337 * ####################################
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339 * ####################################
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342 static ssize_t cgu_read(struct file *file, char *buf, size_t count, loff_t *ppos)
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347 static ssize_t cgu_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
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352 static int cgu_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
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355 struct cgu_clock_rates rates;
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357 if ( _IOC_TYPE(cmd) != CGU_IOC_MAGIC
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358 || _IOC_NR(cmd) >= CGU_IOC_MAXNR )
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361 if ( _IOC_DIR(cmd) & _IOC_READ )
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362 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
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363 else if ( _IOC_DIR(cmd) & _IOC_WRITE )
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364 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
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370 case CGU_GET_CLOCK_RATES:
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371 /* Calculate Clock Rates */
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372 rates.mips0 = cgu_get_mips_clock(0);
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373 rates.mips1 = cgu_get_mips_clock(1);
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374 rates.cpu = cgu_get_cpu_clock();
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375 rates.io_region = cgu_get_io_region_clock();
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376 rates.fpi_bus1 = cgu_get_fpi_bus_clock(1);
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377 rates.fpi_bus2 = cgu_get_fpi_bus_clock(2);
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378 rates.pp32 = cgu_get_pp32_clock();
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379 rates.pci = cgu_get_pci_clock();
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380 rates.ethernet = cgu_get_ethernet_clock();
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381 rates.usb = cgu_get_usb_clock();
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382 rates.clockout0 = cgu_get_clockout(0);
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383 rates.clockout1 = cgu_get_clockout(1);
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384 rates.clockout2 = cgu_get_clockout(2);
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385 rates.clockout3 = cgu_get_clockout(3);
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386 /* Copy to User Space */
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387 copy_to_user((char*)arg, (char*)&rates, sizeof(rates));
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398 static int cgu_open(struct inode *inode, struct file *file)
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403 static int cgu_release(struct inode *inode, struct file *file)
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410 * calculate 64-bit multiplication result of two 32-bit unsigned integer
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412 * u32Multiplier1 --- u32 (32-bit), one of the multipliers
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413 * u32Multiplier2 --- u32 (32-bit), the other multiplier
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414 * u32Result --- u32[2], array to retrieve the multiplication result,
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415 * index 0 is high word, index 1 is low word
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419 static inline void uint64_multiply(u32 u32Multiplier1, u32 u32Multiplier2, u32 u32Result[2])
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421 u32 u32Multiplier1LowWord = u32Multiplier1 & 0xFFFF;
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422 u32 u32Multiplier1HighWord = u32Multiplier1 >> 16;
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423 u32 u32Multiplier2LowWord = u32Multiplier2 & 0xFFFF;
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424 u32 u32Multiplier2HighWord = u32Multiplier2 >> 16;
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425 u32 u32Combo1, u32Combo2, u32Combo3, u32Combo4;
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426 u32 u32Word1, u32Word2, u32Word3, u32Word4;
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428 u32Combo1 = u32Multiplier1LowWord * u32Multiplier2LowWord;
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429 u32Combo2 = u32Multiplier1HighWord * u32Multiplier2LowWord;
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430 u32Combo3 = u32Multiplier1LowWord * u32Multiplier2HighWord;
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431 u32Combo4 = u32Multiplier1HighWord * u32Multiplier2HighWord;
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433 u32Word1 = u32Combo1 & 0xFFFF;
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434 u32Word2 = (u32Combo1 >> 16) + (u32Combo2 & 0xFFFF) + (u32Combo3 & 0xFFFF);
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435 u32Word3 = (u32Combo2 >> 16) + (u32Combo3 >> 16) + (u32Combo4 & 0xFFFF) + (u32Word2 >> 16);
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436 u32Word4 = (u32Combo4 >> 16) + (u32Word3 >> 16);
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438 u32Result[0] = (u32Word4 << 16) | u32Word3;
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439 u32Result[1] = (u32Word2 << 16) | u32Word1;
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444 * divide 64-bit unsigned integer with 32-bit unsigned integer
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446 * u32Numerator --- u32[2], index 0 is high word of numerator, while
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447 * index 1 is low word of numerator
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448 * u32Denominator --- u32 (32-bit), the denominator in division, this
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449 * parameter can not be zero, or lead to unpredictable
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451 * pu32Quotient --- u32 *, the pointer to retrieve 32-bit quotient, null
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452 * pointer means ignore quotient
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453 * pu32Residue --- u32 *, the pointer to retrieve 32-bit residue null
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454 * pointer means ignore residue
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458 static inline void uint64_divide(u32 u32Numerator[2], u32 u32Denominator, u32 *pu32Quotient, u32 *pu32Residue)
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460 u32 u32DWord1, u32DWord2, u32DWord3;
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465 u32DWord2 = u32Numerator[0];
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466 u32DWord1 = u32Numerator[1];
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470 for ( i = 0; i < 64; i++ )
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472 u32DWord3 = (u32DWord3 << 1) | (u32DWord2 >> 31);
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473 u32DWord2 = (u32DWord2 << 1) | (u32DWord1 >> 31);
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476 if ( u32DWord3 >= u32Denominator )
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478 u32DWord3 -= u32Denominator;
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482 if ( pu32Quotient )
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483 *pu32Quotient = u32Quotient;
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485 *pu32Residue = u32DWord3;
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490 * common routine to calculate PLL frequency
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492 * num --- u32, numerator
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493 * den --- u32, denominator
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495 * u32 --- frequency the PLL output
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497 static inline u32 cal_dsm(u32 num, u32 den)
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503 uint64_multiply(num, BASIC_INPUT_CLOCK_FREQUENCY, temp);
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504 uint64_divide(temp, den, &ret, &residue);
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505 if ( (residue << 1) >= den )
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513 * calculate PLL frequency following MASH-DSM
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515 * M --- u32, denominator coefficient
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516 * N --- u32, numerator integer coefficient
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517 * K --- u32, numerator fraction coefficient
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519 * u32 --- frequency the PLL output
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521 static inline u32 mash_dsm(u32 M, u32 N, u32 K)
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523 u32 num = ((N + 1) << 10) + K;
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524 u32 den = (M + 1) << 10;
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526 return cal_dsm(num, den);
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531 * calculate PLL frequency following SSFF-DSM (0.25 < fraction < 0.75)
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533 * M --- u32, denominator coefficient
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534 * N --- u32, numerator integer coefficient
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535 * K --- u32, numerator fraction coefficient
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537 * u32 --- frequency the PLL output
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539 static inline u32 ssff_dsm_1(u32 M, u32 N, u32 K)
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541 u32 num = ((N + 1) << 11) + K + 512;
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542 u32 den = (M + 1) << 11;
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544 return cal_dsm(num, den);
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549 * calculate PLL frequency following SSFF-DSM
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550 * (fraction < 0.125 || fraction > 0.875)
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552 * M --- u32, denominator coefficient
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553 * N --- u32, numerator integer coefficient
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554 * K --- u32, numerator fraction coefficient
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556 * u32 --- frequency the PLL output
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558 static inline u32 ssff_dsm_2(u32 M, u32 N, u32 K)
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560 u32 num = K >= 512 ? ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
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561 u32 den = (M + 1) << 12;
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563 return cal_dsm(num, den);
\r
568 * calculate PLL frequency
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570 * M --- u32, denominator coefficient
\r
571 * N --- u32, numerator integer coefficient
\r
572 * K --- u32, numerator fraction coefficient
\r
573 * dsmsel --- int, 0: MASH-DSM, 1: SSFF-DSM
\r
574 * phase_div_en --- int, 0: 0.25 < fraction < 0.75
\r
575 * 1: fraction < 0.125 || fraction > 0.875
\r
577 * u32 --- frequency the PLL output
\r
579 static inline u32 dsm(u32 M, u32 N, u32 K, int dsmsel, int phase_div_en)
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582 return mash_dsm(M, N, K);
\r
584 if ( !phase_div_en )
\r
585 return ssff_dsm_1(M, N, K);
\r
587 return ssff_dsm_2(M, N, K);
\r
592 * get oscillate frequency of PLL0
\r
596 * u32 --- frequency of PLL0 Fosc
\r
598 static inline u32 cgu_get_pll0_fosc(void)
\r
600 return CGU_PLL_SR0_PLLB ? BASIC_INPUT_CLOCK_FREQUENCY : dsm(CGU_PLL_NMK0_PLLM, CGU_PLL_NMK0_PLLN, CGU_PLL_NMK0_PLLK, CGU_PLL_SR0_DSMSEL, CGU_PLL_SR0_PHASE_DIV_EN);
\r
605 * get output frequency of PLL0 phase shifter
\r
609 * u32 --- frequency of PLL0 Fps
\r
611 static inline u32 cgu_get_pll0_fps(void)
\r
613 register u32 fps = cgu_get_pll0_fosc();
\r
615 switch ( CGU_PLL_SR0_PLLPSE )
\r
619 fps = ((fps << 1) + 1) / 3; break;
\r
622 fps = ((fps << 2) + 2) / 5; break;
\r
625 fps = ((fps << 1) + 3) / 7;
\r
632 * get output frequency of PLL0 output divider
\r
636 * u32 --- frequency of PLL0 Fdiv
\r
638 static inline u32 cgu_get_pll0_fdiv(void)
\r
640 register u32 fdiv = cgu_get_pll0_fosc();
\r
642 if ( CGU_PLL_SR0_PLLDEN )
\r
643 fdiv = (fdiv + (CGU_PLL_SR0_PLLDIV + 1) / 2) / (CGU_PLL_SR0_PLLDIV + 1);
\r
649 * get oscillate frequency of PLL1
\r
653 * u32 --- frequency of PLL1 Fosc
\r
655 static inline u32 cgu_get_pll1_fosc(void)
\r
657 return CGU_PLL_SR1_PLLB ? BASIC_INPUT_CLOCK_FREQUENCY : dsm(CGU_PLL_NMK1_PLLM, CGU_PLL_NMK1_PLLN, CGU_PLL_NMK1_PLLK, CGU_PLL_SR1_DSMSEL, CGU_PLL_SR1_PHASE_DIV_EN);
\r
662 * get output frequency of PLL1 phase shifter
\r
666 * u32 --- frequency of PLL1 Fps
\r
668 static inline u32 cgu_get_pll1_fps(void)
\r
670 register u32 fps = cgu_get_pll1_fosc();
\r
672 switch ( CGU_PLL_SR1_PLLPSE )
\r
676 fps = ((fps << 1) + 1) / 3; break;
\r
679 fps = ((fps << 2) + 2) / 5; break;
\r
682 fps = ((fps << 1) + 3) / 7;
\r
689 * get output frequency of PLL1 output divider
\r
693 * u32 --- frequency of PLL1 Fdiv
\r
695 static inline u32 cgu_get_pll1_fdiv(void)
\r
697 register u32 fdiv = cgu_get_pll1_fosc();
\r
699 if ( CGU_PLL_SR1_PLLDEN )
\r
700 fdiv = (fdiv + (CGU_PLL_SR1_PLLDIV + 1) / 2) / (CGU_PLL_SR1_PLLDIV + 1);
\r
706 * get oscillate frequency of PLL2
\r
710 * u32 --- frequency of PLL2 Fosc
\r
712 static inline u32 cgu_get_pll2_fosc(void)
\r
718 uint64_multiply((CGU_PLL_SR2_PLLN + 1) * 8, cgu_get_pll0_fdiv(), temp);
\r
719 uint64_divide(temp, CGU_PLL_SR2_PLLM + 1, &ret, &residue);
\r
720 if ( (residue << 1) >= CGU_PLL_SR2_PLLM )
\r
728 * get output frequency of PLL2 phase shifter
\r
732 * u32 --- frequency of PLL2 Fps
\r
734 static inline u32 cgu_get_pll2_fps(void)
\r
736 register u32 fps = cgu_get_pll2_fosc();
\r
738 if ( CGU_PLL_SR2_PLLPE )
\r
740 if ( CGU_PLL_SR2_PLLPS )
\r
742 fps = ((fps << 3) + 4) / 9;
\r
745 fps = ((fps << 2) + 2) / 5;
\r
753 * ####################################
\r
755 * ####################################
\r
760 * get frequency of MIPS (0: core, 1: DSP)
\r
762 * cpu --- int, 0: core, 1: DSP
\r
764 * u32 --- frequency of MIPS coprocessor (0: core, 1: DSP)
\r
766 u32 cgu_get_mips_clock(int cpu)
\r
768 register u32 ret = cgu_get_pll0_fosc();
\r
771 ret = (ret + (CGU_CRD_CRD >> 1)) / (CGU_CRD_CRD + 1);
\r
772 if ( cpu == 0 && CGU_CRD_CRD1 )
\r
773 ret >>= CGU_CRD_CRD1;
\r
779 * get frequency of MIPS core
\r
783 * u32 --- frequency of MIPS core
\r
785 u32 cgu_get_cpu_clock(void)
\r
787 return cgu_get_mips_clock(0);
\r
792 * get frequency of sub-system and memory controller
\r
796 * u32 --- frequency of sub-system and memory controller
\r
798 u32 cgu_get_io_region_clock(void)
\r
800 register u32 ret = (CGU_MUX_SUB_SYS > 4) ? cgu_get_pll0_fosc() : cgu_get_mips_clock(1);
\r
802 switch ( CGU_MUX_SUB_SYS )
\r
808 ret = (ret + 1) >> 1; break;
\r
810 ret = (ret + 1) / 3; break;
\r
812 ret = (ret + 2) >> 2; break;
\r
814 ret = ((ret << 1) + 1) / 3; break;
\r
816 ret = ((ret << 1) + 2) / 5;
\r
824 * get frequency of FPI bus
\r
826 * fpi --- int, 1: FPI bus 1 (FBS1/Fast FPI Bus), 2: FPI bus 2 (FBS2)
\r
828 * u32 --- frequency of FPI bus
\r
830 u32 cgu_get_fpi_bus_clock(int fpi)
\r
832 register u32 ret = cgu_get_io_region_clock();
\r
841 * get frequency of PP32 processor
\r
845 * u32 --- frequency of PP32 processor
\r
847 u32 cgu_get_pp32_clock(void)
\r
851 switch ( CGU_MUX_PP32 )
\r
855 ret = ((cgu_get_pll2_fosc() << 2) + 2) / 5; break;
\r
857 ret = ((cgu_get_pll2_fosc() << 3) + 4) / 9; break;
\r
859 ret = cgu_get_fpi_bus_clock(1); break;
\r
861 ret = cgu_get_mips_clock(1);
\r
869 * get frequency of PCI bus
\r
873 * u32 --- frequency of PCI bus
\r
875 u32 cgu_get_pci_clock(void)
\r
877 register u32 ret = 0;
\r
879 if ( !CGU_IF_CLK_PCIS )
\r
881 ret = cgu_get_pll2_fosc();
\r
882 if ( CGU_IF_CLK_PCIF )
\r
883 ret = (ret + 2) / 5;
\r
885 ret = (ret + 4) / 9;
\r
893 * get frequency of ethernet module (MII)
\r
897 * u32 --- frequency of ethernet module
\r
899 u32 cgu_get_ethernet_clock(void)
\r
901 register u32 ret = 0;
\r
903 if ( !CGU_IF_CLK_MIICS )
\r
905 ret = cgu_get_pll2_fosc();
\r
906 if ( CGU_MUX_MII_CLK )
\r
907 ret = (ret + 3) / 6;
\r
909 ret = (ret + 6) / 12;
\r
917 * get frequency of USB
\r
921 * u32 --- frequency of USB
\r
923 u32 cgu_get_usb_clock(void)
\r
925 return CGU_IF_CLK_USBCS ? 12000000 : (cgu_get_pll2_fosc() + 12) / 25;
\r
930 * get frequency of CLK_OUT pin
\r
932 * clkout --- int, clock out pin number
\r
934 * u32 --- frequency of CLK_OUT pin
\r
936 u32 cgu_get_clockout(int clkout)
\r
938 u32 fosc1 = cgu_get_pll1_fosc();
\r
939 u32 fosc2 = cgu_get_pll2_fosc();
\r
941 if ( clkout > 3 || clkout < 0 )
\r
944 switch ( ((u32)clkout << 2) | GET_BITS(*DANUBE_CGU_IF_CLK, 21 + clkout * 2, 20 + clkout * 2) )
\r
946 case 0: /* 32.768KHz */
\r
948 return (fosc1 + 6000) / 12000;
\r
949 case 1: /* 1.536MHz */
\r
950 return (fosc1 + 128) / 256;
\r
951 case 2: /* 2.5MHz */
\r
952 return (fosc2 + 60) / 120;
\r
953 case 3: /* 12MHz */
\r
956 return (fosc2 + 12) / 25;
\r
957 case 4: /* 40MHz */
\r
958 return (fosc2 * 2 + 7) / 15;
\r
959 case 6: /* 24MHz */
\r
960 return (fosc2 * 2 + 12) / 25;
\r
961 case 7: /* 48MHz */
\r
962 return (fosc2 * 4 + 12) / 25;
\r
963 case 8: /* 25MHz */
\r
965 return (fosc2 + 6) / 12;
\r
966 case 9: /* 50MHz */
\r
968 return (fosc2 + 3) / 6;
\r
969 case 10:/* 30MHz */
\r
970 return (fosc2 + 5) / 10;
\r
971 case 11:/* 60MHz */
\r
972 return (fosc2 + 2) / 5;
\r
980 * ####################################
\r
982 * ####################################
\r
992 * else --- failure, usually it is negative value of error code
\r
994 int __init danube_cgu_init(void)
\r
998 ret = misc_register(&cgu_miscdev);
\r
1001 printk(KERN_ERR "cgu: can't misc_register\n");
\r
1005 printk(KERN_INFO "cgu: misc_register on minor = %d\n", cgu_miscdev.minor);
\r
1008 * initialize fake registers to do testing on Amazon
\r
1010 #if defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
\r
1011 #ifdef DEBUG_PRINT_INFO
\r
1012 #undef DEBUG_PRINT_INFO
\r
1014 #define DEBUG_PRINT_INFO 1
\r
1016 *DANUBE_CGU_DIV = 0x00010019;
\r
1017 *DANUBE_CGU_PLL_NMK0 = 0x416002C3;
\r
1018 *DANUBE_CGU_PLL_SR0 = 0x74000013;
\r
1019 *DANUBE_CGU_PLL_NMK1 = 0x4C60009C;
\r
1020 *DANUBE_CGU_PLL_SR1 = 0x54000013;
\r
1021 *DANUBE_CGU_PLL_SR2 = 0x58890013;
\r
1022 *DANUBE_CGU_IF_CLK = 0x00000000;
\r
1023 *DANUBE_CGU_OSC_CTRL = 0x00000000;
\r
1024 *DANUBE_CGU_SMD = 0x00000000;
\r
1025 *DANUBE_CGU_CRD = 0x00010000;
\r
1026 *DANUBE_CGU_CT1SR = 0x00000000;
\r
1027 *DANUBE_CGU_CT2SR = CGU_PLL_NMK1_PLLK;
\r
1028 *DANUBE_CGU_PCMCR = 0x00000000;
\r
1029 *DANUBE_CGU_MUX = 0x00000008;
\r
1030 #endif // defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
\r
1033 * for testing only
\r
1035 #if defined(DEBUG_PRINT_INFO) && DEBUG_PRINT_INFO
\r
1036 printk("pll0 N = %d, M = %d, K = %d, DIV = %d\n", CGU_PLL_NMK0_PLLN, CGU_PLL_NMK0_PLLM, CGU_PLL_NMK0_PLLK, CGU_PLL_SR0_PLLDIV);
\r
1037 printk("pll1 N = %d, M = %d, K = %d, DIV = %d\n", CGU_PLL_NMK1_PLLN, CGU_PLL_NMK1_PLLM, CGU_PLL_NMK1_PLLK, CGU_PLL_SR1_PLLDIV);
\r
1038 printk("pll2 N = %d, M = %d, DIV = %d\n", CGU_PLL_SR2_PLLN, CGU_PLL_SR2_PLLM, CGU_PLL_SR2_PLLDIV);
\r
1039 printk("pll0_fosc = %d\n", cgu_get_pll0_fosc());
\r
1040 printk("pll0_fps = %d\n", cgu_get_pll0_fps());
\r
1041 printk("pll0_fdiv = %d\n", cgu_get_pll0_fdiv());
\r
1042 printk("pll1_fosc = %d\n", cgu_get_pll1_fosc());
\r
1043 printk("pll1_fps = %d\n", cgu_get_pll1_fps());
\r
1044 printk("pll1_fdiv = %d\n", cgu_get_pll1_fdiv());
\r
1045 printk("pll2_fosc = %d\n", cgu_get_pll2_fosc());
\r
1046 printk("pll2_fps = %d\n", cgu_get_pll2_fps());
\r
1047 printk("mips0 clock = %d\n", cgu_get_mips_clock(0));
\r
1048 printk("mips1 clock = %d\n", cgu_get_mips_clock(1));
\r
1049 printk("cpu clock = %d\n", cgu_get_cpu_clock());
\r
1050 printk("IO region = %d\n", cgu_get_io_region_clock());
\r
1051 printk("FPI bus 1 = %d\n", cgu_get_fpi_bus_clock(1));
\r
1052 printk("FPI bus 2 = %d\n", cgu_get_fpi_bus_clock(2));
\r
1053 printk("PP32 clock = %d\n", cgu_get_pp32_clock());
\r
1054 printk("PCI clock = %d\n", cgu_get_pci_clock());
\r
1055 printk("Ethernet = %d\n", cgu_get_ethernet_clock());
\r
1056 printk("USB clock = %d\n", cgu_get_usb_clock());
\r
1057 printk("Clockout0 = %d\n", cgu_get_clockout(0));
\r
1058 printk("Clockout1 = %d\n", cgu_get_clockout(1));
\r
1059 printk("Clockout2 = %d\n", cgu_get_clockout(2));
\r
1060 printk("Clockout3 = %d\n", cgu_get_clockout(3));
\r
1061 #endif // defined(DEBUG_PRINT_INFO) && DEBUG_PRINT_INFO
\r
1068 * deregister device
\r
1074 void __exit danube_cgu_exit(void)
\r
1078 ret = misc_deregister(&cgu_miscdev);
\r
1080 printk(KERN_ERR "cgu: can't misc_deregister, get error number %d\n", -ret);
\r
1082 printk(KERN_INFO "cgu: misc_deregister successfully\n");
\r
1085 module_init(danube_cgu_init);
\r
1086 module_exit(danube_cgu_exit);
\r