2 * pcicfg.h: PCI configuration constants and structures.
4 * Copyright 2004, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18 /* The following inside ifndef's so we don't collide with NTDDK.H */
20 #define PCI_MAX_BUS 0x100
22 #ifndef PCI_MAX_DEVICES
23 #define PCI_MAX_DEVICES 0x20
25 #ifndef PCI_MAX_FUNCTION
26 #define PCI_MAX_FUNCTION 0x8
29 #ifndef PCI_INVALID_VENDORID
30 #define PCI_INVALID_VENDORID 0xffff
32 #ifndef PCI_INVALID_DEVICEID
33 #define PCI_INVALID_DEVICEID 0xffff
37 /* Convert between bus-slot-function-register and config addresses */
39 #define PCICFG_BUS_SHIFT 16 /* Bus shift */
40 #define PCICFG_SLOT_SHIFT 11 /* Slot shift */
41 #define PCICFG_FUN_SHIFT 8 /* Function shift */
42 #define PCICFG_OFF_SHIFT 0 /* Bus shift */
44 #define PCICFG_BUS_MASK 0xff /* Bus mask */
45 #define PCICFG_SLOT_MASK 0x1f /* Slot mask */
46 #define PCICFG_FUN_MASK 7 /* Function mask */
47 #define PCICFG_OFF_MASK 0xff /* Bus mask */
49 #define PCI_CONFIG_ADDR(b, s, f, o) \
50 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
51 | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
52 | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
53 | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
55 #define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
56 #define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
57 #define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
58 #define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
61 /* The actual config space */
67 #define PCR_RSVDA_MAX 2
69 typedef struct _pci_config_regs {
70 unsigned short vendor;
71 unsigned short device;
72 unsigned short command;
73 unsigned short status;
75 unsigned char prog_if;
76 unsigned char sub_class;
77 unsigned char base_class;
78 unsigned char cache_line_size;
79 unsigned char latency_timer;
80 unsigned char header_type;
82 unsigned long base[PCI_BAR_MAX];
83 unsigned long cardbus_cis;
84 unsigned short subsys_vendor;
85 unsigned short subsys_id;
86 unsigned long baserom;
87 unsigned long rsvd_a[PCR_RSVDA_MAX];
88 unsigned char int_line;
89 unsigned char int_pin;
90 unsigned char min_gnt;
91 unsigned char max_lat;
92 unsigned char dev_dep[192];
95 #define SZPCR (sizeof (pci_config_regs))
96 #define MINSZPCR 64 /* offsetof (dev_dep[0] */
98 /* A structure for the config registers is nice, but in most
99 * systems the config space is not memory mapped, so we need
100 * filed offsetts. :-(
102 #define PCI_CFG_VID 0
103 #define PCI_CFG_DID 2
104 #define PCI_CFG_CMD 4
105 #define PCI_CFG_STAT 6
106 #define PCI_CFG_REV 8
107 #define PCI_CFG_PROGIF 9
108 #define PCI_CFG_SUBCL 0xa
109 #define PCI_CFG_BASECL 0xb
110 #define PCI_CFG_CLSZ 0xc
111 #define PCI_CFG_LATTIM 0xd
112 #define PCI_CFG_HDR 0xe
113 #define PCI_CFG_BIST 0xf
114 #define PCI_CFG_BAR0 0x10
115 #define PCI_CFG_BAR1 0x14
116 #define PCI_CFG_BAR2 0x18
117 #define PCI_CFG_BAR3 0x1c
118 #define PCI_CFG_BAR4 0x20
119 #define PCI_CFG_BAR5 0x24
120 #define PCI_CFG_CIS 0x28
121 #define PCI_CFG_SVID 0x2c
122 #define PCI_CFG_SSID 0x2e
123 #define PCI_CFG_ROMBAR 0x30
124 #define PCI_CFG_INT 0x3c
125 #define PCI_CFG_PIN 0x3d
126 #define PCI_CFG_MINGNT 0x3e
127 #define PCI_CFG_MAXLAT 0x3f
129 /* Classes and subclasses */
145 PCI_CLASS_INTELLIGENT = 0xe,
158 PCI_DASDI_OTHER = 0x80
159 } pci_dasdi_subclasses;
167 } pci_net_subclasses;
173 PCI_DISPLAY_OTHER = 0x80
174 } pci_display_subclasses;
180 PCI_MEDIA_OTHER = 0x80
181 } pci_mmedia_subclasses;
186 PCI_MEMORY_OTHER = 0x80
187 } pci_memory_subclasses;
199 PCI_BRIDGE_OTHER = 0x80
200 } pci_bridge_subclasses;
207 PCI_COMM_OTHER = 0x80
208 } pci_comm_subclasses;
215 PCI_BASE_PCI_HOTPLUG,
216 PCI_BASE_OTHER = 0x80
217 } pci_base_subclasses;
225 PCI_INPUT_OTHER = 0x80
226 } pci_input_subclasses;
230 PCI_DOCK_OTHER = 0x80
231 } pci_dock_subclasses;
237 PCI_CPU_ALPHA = 0x10,
238 PCI_CPU_POWERPC = 0x20,
240 PCI_CPU_COPROC = 0x40,
242 } pci_cpu_subclasses;
251 PCI_SERIAL_OTHER = 0x80
252 } pci_serial_subclasses;
256 } pci_intelligent_subclasses;
263 PCI_SATELLITE_OTHER = 0x80
264 } pci_satellite_subclasses;
268 PCI_CRYPT_ENTERTAINMENT,
269 PCI_CRYPT_OTHER = 0x80
270 } pci_crypt_subclasses;
275 } pci_dsp_subclasses;
285 /* Overlay for a PCI-to-PCI bridge */
287 #define PPB_RSVDA_MAX 2
288 #define PPB_RSVDD_MAX 8
290 typedef struct _ppb_config_regs {
291 unsigned short vendor;
292 unsigned short device;
293 unsigned short command;
294 unsigned short status;
295 unsigned char rev_id;
296 unsigned char prog_if;
297 unsigned char sub_class;
298 unsigned char base_class;
299 unsigned char cache_line_size;
300 unsigned char latency_timer;
301 unsigned char header_type;
303 unsigned long rsvd_a[PPB_RSVDA_MAX];
304 unsigned char prim_bus;
305 unsigned char sec_bus;
306 unsigned char sub_bus;
307 unsigned char sec_lat;
308 unsigned char io_base;
309 unsigned char io_lim;
310 unsigned short sec_status;
311 unsigned short mem_base;
312 unsigned short mem_lim;
313 unsigned short pf_mem_base;
314 unsigned short pf_mem_lim;
315 unsigned long pf_mem_base_hi;
316 unsigned long pf_mem_lim_hi;
317 unsigned short io_base_hi;
318 unsigned short io_lim_hi;
319 unsigned short subsys_vendor;
320 unsigned short subsys_id;
321 unsigned long rsvd_b;
322 unsigned char rsvd_c;
323 unsigned char int_pin;
324 unsigned short bridge_ctrl;
325 unsigned char chip_ctrl;
326 unsigned char diag_ctrl;
327 unsigned short arb_ctrl;
328 unsigned long rsvd_d[PPB_RSVDD_MAX];
329 unsigned char dev_dep[192];
332 /* Eveything below is BRCM HND proprietary */
334 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
335 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
336 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */
337 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
338 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
339 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
340 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
341 #define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
342 #define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
343 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
344 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
345 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
347 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
348 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
351 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
354 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
355 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
356 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
358 /* PCI_SPROM_CONTROL */
359 #define SPROM_BLANK 0x04 /* indicating a blank sprom */
360 #define SPROM_WRITEEN 0x10 /* sprom write enable */
361 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
363 #define SPROM_SIZE 256 /* sprom size in 16-bit */
364 #define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
366 /* PCI_CFG_CMD_STAT */
367 #define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */