CC: ar71xx: fix ath79_soc_rev value for QCA9531 ver. 2

[15.05/openwrt.git] / target / linux / ar71xx / patches-3.18 / 707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 5041619..f3b4446 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -292,12 +292,13 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  
        id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
        major = id & REV_ID_MAJOR_MASK;
-@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
+@@ -151,6 +152,17 @@ static void __init ath79_detect_sys_type
                rev = id & AR934X_REV_ID_REVISION_MASK;
                break;
  
 +      case REV_ID_MAJOR_QCA9533_V2:
 +              ver = 2;
++              ath79_soc_rev = 2;
 +              /* drop through */
 +
 +      case REV_ID_MAJOR_QCA9533:
@@ -309,9 +310,13 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        case REV_ID_MAJOR_QCA9556:
                ath79_soc = ATH79_SOC_QCA9556;
                chip = "9556";
-@@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
+@@ -167,11 +179,12 @@ static void __init ath79_detect_sys_type
+               panic("ath79: unknown SoC, id:0x%08x", id);
+       }
  
-       ath79_soc_rev = rev;
+-      ath79_soc_rev = rev;
++      if (ver == 1)
++              ath79_soc_rev = rev;
  
 -      if (soc_is_qca955x())
 -              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",