target/linux/sunxi/patches-3.13/260-spi-add-a31-spi-driver.patch

   1 From 3558fe900e8af6c3bfadeff24a12ffb19ac9b108 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Wed, 5 Feb 2014 14:05:05 +0100
   4 Subject: [PATCH 1/2] spi: sunxi: Add Allwinner A31 SPI controller driver
   5
   6 The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
   7 SoCs.
   8
   9 It supports DMA, but the driver only does PIO for now, and DMA will be
  10 supported eventually.
  11
  12 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 Signed-off-by: Mark Brown <broonie@linaro.org>
  14 ---
  15  .../devicetree/bindings/spi/spi-sun6i.txt          |  24 +
  16  drivers/spi/Kconfig                                |   6 +
  17  drivers/spi/Makefile                               |   1 +
  18  drivers/spi/spi-sun6i.c                            | 483 +++++++++++++++++++++
  19  4 files changed, 514 insertions(+)
  20  create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt
  21  create mode 100644 drivers/spi/spi-sun6i.c
  22
  23 diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
  24 new file mode 100644
  25 index 0000000..21de73d
  26 --- /dev/null
  27 +++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
  28 @@ -0,0 +1,24 @@
  29 +Allwinner A31 SPI controller
  30 +
  31 +Required properties:
  32 +- compatible: Should be "allwinner,sun6i-a31-spi".
  33 +- reg: Should contain register location and length.
  34 +- interrupts: Should contain interrupt.
  35 +- clocks: phandle to the clocks feeding the SPI controller. Two are
  36 +          needed:
  37 +  - "ahb": the gated AHB parent clock
  38 +  - "mod": the parent module clock
  39 +- clock-names: Must contain the clock names described just above
  40 +- resets: phandle to the reset controller asserting this device in
  41 +          reset
  42 +
  43 +Example:
  44 +
  45 +spi1: spi@01c69000 {
  46 +       compatible = "allwinner,sun6i-a31-spi";
  47 +       reg = <0x01c69000 0x1000>;
  48 +       interrupts = <0 66 4>;
  49 +       clocks = <&ahb1_gates 21>, <&spi1_clk>;
  50 +       clock-names = "ahb", "mod";
  51 +       resets = <&ahb1_rst 21>;
  52 +};
  53 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  54 index ba9310b..7cfe0ee 100644
  55 --- a/drivers/spi/Kconfig
  56 +++ b/drivers/spi/Kconfig
  57 @@ -446,6 +446,12 @@ config SPI_SIRF
  58         help
  59           SPI driver for CSR SiRFprimaII SoCs
  60
  61 +config SPI_SUN6I
  62 +       tristate "Allwinner A31 SPI controller"
  63 +       depends on ARCH_SUNXI || COMPILE_TEST
  64 +       help
  65 +         This enables using the SPI controller on the Allwinner A31 SoCs.
  66 +
  67  config SPI_MXS
  68         tristate "Freescale MXS SPI controller"
  69         depends on ARCH_MXS
  70 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  71 index 95af48d..13b6ccf 100644
  72 --- a/drivers/spi/Makefile
  73 +++ b/drivers/spi/Makefile
  74 @@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI)             += spi-sh-hspi.o
  75  obj-$(CONFIG_SPI_SH_MSIOF)             += spi-sh-msiof.o
  76  obj-$(CONFIG_SPI_SH_SCI)               += spi-sh-sci.o
  77  obj-$(CONFIG_SPI_SIRF)         += spi-sirf.o
  78 +obj-$(CONFIG_SPI_SUN6I)                        += spi-sun6i.o
  79  obj-$(CONFIG_SPI_TEGRA114)             += spi-tegra114.o
  80  obj-$(CONFIG_SPI_TEGRA20_SFLASH)       += spi-tegra20-sflash.o
  81  obj-$(CONFIG_SPI_TEGRA20_SLINK)                += spi-tegra20-slink.o
  82 diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
  83 new file mode 100644
  84 index 0000000..94d38d0
  85 --- /dev/null
  86 +++ b/drivers/spi/spi-sun6i.c
  87 @@ -0,0 +1,483 @@
  88 +/*
  89 + * Copyright (C) 2012 - 2014 Allwinner Tech
  90 + * Pan Nan <pannan@allwinnertech.com>
  91 + *
  92 + * Copyright (C) 2014 Maxime Ripard
  93 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  94 + *
  95 + * This program is free software; you can redistribute it and/or
  96 + * modify it under the terms of the GNU General Public License as
  97 + * published by the Free Software Foundation; either version 2 of
  98 + * the License, or (at your option) any later version.
  99 + */
 100 +
 101 +#include <linux/clk.h>
 102 +#include <linux/delay.h>
 103 +#include <linux/device.h>
 104 +#include <linux/interrupt.h>
 105 +#include <linux/io.h>
 106 +#include <linux/module.h>
 107 +#include <linux/platform_device.h>
 108 +#include <linux/pm_runtime.h>
 109 +#include <linux/reset.h>
 110 +#include <linux/workqueue.h>
 111 +
 112 +#include <linux/spi/spi.h>
 113 +
 114 +#define SUN6I_FIFO_DEPTH               128
 115 +
 116 +#define SUN6I_GBL_CTL_REG              0x04
 117 +#define SUN6I_GBL_CTL_BUS_ENABLE               BIT(0)
 118 +#define SUN6I_GBL_CTL_MASTER                   BIT(1)
 119 +#define SUN6I_GBL_CTL_TP                       BIT(7)
 120 +#define SUN6I_GBL_CTL_RST                      BIT(31)
 121 +
 122 +#define SUN6I_TFR_CTL_REG              0x08
 123 +#define SUN6I_TFR_CTL_CPHA                     BIT(0)
 124 +#define SUN6I_TFR_CTL_CPOL                     BIT(1)
 125 +#define SUN6I_TFR_CTL_SPOL                     BIT(2)
 126 +#define SUN6I_TFR_CTL_CS_MASK                  0x3
 127 +#define SUN6I_TFR_CTL_CS(cs)                   (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4)
 128 +#define SUN6I_TFR_CTL_CS_MANUAL                        BIT(6)
 129 +#define SUN6I_TFR_CTL_CS_LEVEL                 BIT(7)
 130 +#define SUN6I_TFR_CTL_DHB                      BIT(8)
 131 +#define SUN6I_TFR_CTL_FBS                      BIT(12)
 132 +#define SUN6I_TFR_CTL_XCH                      BIT(31)
 133 +
 134 +#define SUN6I_INT_CTL_REG              0x10
 135 +#define SUN6I_INT_CTL_RF_OVF                   BIT(8)
 136 +#define SUN6I_INT_CTL_TC                       BIT(12)
 137 +
 138 +#define SUN6I_INT_STA_REG              0x14
 139 +
 140 +#define SUN6I_FIFO_CTL_REG             0x18
 141 +#define SUN6I_FIFO_CTL_RF_RST                  BIT(15)
 142 +#define SUN6I_FIFO_CTL_TF_RST                  BIT(31)
 143 +
 144 +#define SUN6I_FIFO_STA_REG             0x1c
 145 +#define SUN6I_FIFO_STA_RF_CNT_MASK             0x7f
 146 +#define SUN6I_FIFO_STA_RF_CNT_BITS             0
 147 +#define SUN6I_FIFO_STA_TF_CNT_MASK             0x7f
 148 +#define SUN6I_FIFO_STA_TF_CNT_BITS             16
 149 +
 150 +#define SUN6I_CLK_CTL_REG              0x24
 151 +#define SUN6I_CLK_CTL_CDR2_MASK                        0xff
 152 +#define SUN6I_CLK_CTL_CDR2(div)                        (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
 153 +#define SUN6I_CLK_CTL_CDR1_MASK                        0xf
 154 +#define SUN6I_CLK_CTL_CDR1(div)                        (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
 155 +#define SUN6I_CLK_CTL_DRS                      BIT(12)
 156 +
 157 +#define SUN6I_BURST_CNT_REG            0x30
 158 +#define SUN6I_BURST_CNT(cnt)                   ((cnt) & 0xffffff)
 159 +
 160 +#define SUN6I_XMIT_CNT_REG             0x34
 161 +#define SUN6I_XMIT_CNT(cnt)                    ((cnt) & 0xffffff)
 162 +
 163 +#define SUN6I_BURST_CTL_CNT_REG                0x38
 164 +#define SUN6I_BURST_CTL_CNT_STC(cnt)           ((cnt) & 0xffffff)
 165 +
 166 +#define SUN6I_TXDATA_REG               0x200
 167 +#define SUN6I_RXDATA_REG               0x300
 168 +
 169 +struct sun6i_spi {
 170 +       struct spi_master       *master;
 171 +       void __iomem            *base_addr;
 172 +       struct clk              *hclk;
 173 +       struct clk              *mclk;
 174 +       struct reset_control    *rstc;
 175 +
 176 +       struct completion       done;
 177 +
 178 +       const u8                *tx_buf;
 179 +       u8                      *rx_buf;
 180 +       int                     len;
 181 +};
 182 +
 183 +static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
 184 +{
 185 +       return readl(sspi->base_addr + reg);
 186 +}
 187 +
 188 +static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
 189 +{
 190 +       writel(value, sspi->base_addr + reg);
 191 +}
 192 +
 193 +static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
 194 +{
 195 +       u32 reg, cnt;
 196 +       u8 byte;
 197 +
 198 +       /* See how much data is available */
 199 +       reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 200 +       reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
 201 +       cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
 202 +
 203 +       if (len > cnt)
 204 +               len = cnt;
 205 +
 206 +       while (len--) {
 207 +               byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
 208 +               if (sspi->rx_buf)
 209 +                       *sspi->rx_buf++ = byte;
 210 +       }
 211 +}
 212 +
 213 +static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
 214 +{
 215 +       u8 byte;
 216 +
 217 +       if (len > sspi->len)
 218 +               len = sspi->len;
 219 +
 220 +       while (len--) {
 221 +               byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 222 +               writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
 223 +               sspi->len--;
 224 +       }
 225 +}
 226 +
 227 +static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
 228 +{
 229 +       struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
 230 +       u32 reg;
 231 +
 232 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 233 +       reg &= ~SUN6I_TFR_CTL_CS_MASK;
 234 +       reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
 235 +
 236 +       if (enable)
 237 +               reg |= SUN6I_TFR_CTL_CS_LEVEL;
 238 +       else
 239 +               reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
 240 +
 241 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 242 +}
 243 +
 244 +
 245 +static int sun6i_spi_transfer_one(struct spi_master *master,
 246 +                                 struct spi_device *spi,
 247 +                                 struct spi_transfer *tfr)
 248 +{
 249 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 250 +       unsigned int mclk_rate, div, timeout;
 251 +       unsigned int tx_len = 0;
 252 +       int ret = 0;
 253 +       u32 reg;
 254 +
 255 +       /* We don't support transfer larger than the FIFO */
 256 +       if (tfr->len > SUN6I_FIFO_DEPTH)
 257 +               return -EINVAL;
 258 +
 259 +       reinit_completion(&sspi->done);
 260 +       sspi->tx_buf = tfr->tx_buf;
 261 +       sspi->rx_buf = tfr->rx_buf;
 262 +       sspi->len = tfr->len;
 263 +
 264 +       /* Clear pending interrupts */
 265 +       sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
 266 +
 267 +       /* Reset FIFO */
 268 +       sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 269 +                       SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
 270 +
 271 +       /*
 272 +        * Setup the transfer control register: Chip Select,
 273 +        * polarities, etc.
 274 +        */
 275 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 276 +
 277 +       if (spi->mode & SPI_CPOL)
 278 +               reg |= SUN6I_TFR_CTL_CPOL;
 279 +       else
 280 +               reg &= ~SUN6I_TFR_CTL_CPOL;
 281 +
 282 +       if (spi->mode & SPI_CPHA)
 283 +               reg |= SUN6I_TFR_CTL_CPHA;
 284 +       else
 285 +               reg &= ~SUN6I_TFR_CTL_CPHA;
 286 +
 287 +       if (spi->mode & SPI_LSB_FIRST)
 288 +               reg |= SUN6I_TFR_CTL_FBS;
 289 +       else
 290 +               reg &= ~SUN6I_TFR_CTL_FBS;
 291 +
 292 +       /*
 293 +        * If it's a TX only transfer, we don't want to fill the RX
 294 +        * FIFO with bogus data
 295 +        */
 296 +       if (sspi->rx_buf)
 297 +               reg &= ~SUN6I_TFR_CTL_DHB;
 298 +       else
 299 +               reg |= SUN6I_TFR_CTL_DHB;
 300 +
 301 +       /* We want to control the chip select manually */
 302 +       reg |= SUN6I_TFR_CTL_CS_MANUAL;
 303 +
 304 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 305 +
 306 +       /* Ensure that we have a parent clock fast enough */
 307 +       mclk_rate = clk_get_rate(sspi->mclk);
 308 +       if (mclk_rate < (2 * spi->max_speed_hz)) {
 309 +               clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
 310 +               mclk_rate = clk_get_rate(sspi->mclk);
 311 +       }
 312 +
 313 +       /*
 314 +        * Setup clock divider.
 315 +        *
 316 +        * We have two choices there. Either we can use the clock
 317 +        * divide rate 1, which is calculated thanks to this formula:
 318 +        * SPI_CLK = MOD_CLK / (2 ^ cdr)
 319 +        * Or we can use CDR2, which is calculated with the formula:
 320 +        * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 321 +        * Wether we use the former or the latter is set through the
 322 +        * DRS bit.
 323 +        *
 324 +        * First try CDR2, and if we can't reach the expected
 325 +        * frequency, fall back to CDR1.
 326 +        */
 327 +       div = mclk_rate / (2 * spi->max_speed_hz);
 328 +       if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
 329 +               if (div > 0)
 330 +                       div--;
 331 +
 332 +               reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
 333 +       } else {
 334 +               div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
 335 +               reg = SUN6I_CLK_CTL_CDR1(div);
 336 +       }
 337 +
 338 +       sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
 339 +
 340 +       /* Setup the transfer now... */
 341 +       if (sspi->tx_buf)
 342 +               tx_len = tfr->len;
 343 +
 344 +       /* Setup the counters */
 345 +       sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
 346 +       sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
 347 +       sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
 348 +                       SUN6I_BURST_CTL_CNT_STC(tx_len));
 349 +
 350 +       /* Fill the TX FIFO */
 351 +       sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
 352 +
 353 +       /* Enable the interrupts */
 354 +       sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
 355 +
 356 +       /* Start the transfer */
 357 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 358 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
 359 +
 360 +       timeout = wait_for_completion_timeout(&sspi->done,
 361 +                                             msecs_to_jiffies(1000));
 362 +       if (!timeout) {
 363 +               ret = -ETIMEDOUT;
 364 +               goto out;
 365 +       }
 366 +
 367 +       sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
 368 +
 369 +out:
 370 +       sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
 371 +
 372 +       return ret;
 373 +}
 374 +
 375 +static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
 376 +{
 377 +       struct sun6i_spi *sspi = dev_id;
 378 +       u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
 379 +
 380 +       /* Transfer complete */
 381 +       if (status & SUN6I_INT_CTL_TC) {
 382 +               sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
 383 +               complete(&sspi->done);
 384 +               return IRQ_HANDLED;
 385 +       }
 386 +
 387 +       return IRQ_NONE;
 388 +}
 389 +
 390 +static int sun6i_spi_runtime_resume(struct device *dev)
 391 +{
 392 +       struct spi_master *master = dev_get_drvdata(dev);
 393 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 394 +       int ret;
 395 +
 396 +       ret = clk_prepare_enable(sspi->hclk);
 397 +       if (ret) {
 398 +               dev_err(dev, "Couldn't enable AHB clock\n");
 399 +               goto out;
 400 +       }
 401 +
 402 +       ret = clk_prepare_enable(sspi->mclk);
 403 +       if (ret) {
 404 +               dev_err(dev, "Couldn't enable module clock\n");
 405 +               goto err;
 406 +       }
 407 +
 408 +       ret = reset_control_deassert(sspi->rstc);
 409 +       if (ret) {
 410 +               dev_err(dev, "Couldn't deassert the device from reset\n");
 411 +               goto err2;
 412 +       }
 413 +
 414 +       sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
 415 +                       SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
 416 +
 417 +       return 0;
 418 +
 419 +err2:
 420 +       clk_disable_unprepare(sspi->mclk);
 421 +err:
 422 +       clk_disable_unprepare(sspi->hclk);
 423 +out:
 424 +       return ret;
 425 +}
 426 +
 427 +static int sun6i_spi_runtime_suspend(struct device *dev)
 428 +{
 429 +       struct spi_master *master = dev_get_drvdata(dev);
 430 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 431 +
 432 +       reset_control_assert(sspi->rstc);
 433 +       clk_disable_unprepare(sspi->mclk);
 434 +       clk_disable_unprepare(sspi->hclk);
 435 +
 436 +       return 0;
 437 +}
 438 +
 439 +static int sun6i_spi_probe(struct platform_device *pdev)
 440 +{
 441 +       struct spi_master *master;
 442 +       struct sun6i_spi *sspi;
 443 +       struct resource *res;
 444 +       int ret = 0, irq;
 445 +
 446 +       master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
 447 +       if (!master) {
 448 +               dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 449 +               return -ENOMEM;
 450 +       }
 451 +
 452 +       platform_set_drvdata(pdev, master);
 453 +       sspi = spi_master_get_devdata(master);
 454 +
 455 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 456 +       sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
 457 +       if (IS_ERR(sspi->base_addr)) {
 458 +               ret = PTR_ERR(sspi->base_addr);
 459 +               goto err_free_master;
 460 +       }
 461 +
 462 +       irq = platform_get_irq(pdev, 0);
 463 +       if (irq < 0) {
 464 +               dev_err(&pdev->dev, "No spi IRQ specified\n");
 465 +               ret = -ENXIO;
 466 +               goto err_free_master;
 467 +       }
 468 +
 469 +       ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
 470 +                              0, "sun6i-spi", sspi);
 471 +       if (ret) {
 472 +               dev_err(&pdev->dev, "Cannot request IRQ\n");
 473 +               goto err_free_master;
 474 +       }
 475 +
 476 +       sspi->master = master;
 477 +       master->set_cs = sun6i_spi_set_cs;
 478 +       master->transfer_one = sun6i_spi_transfer_one;
 479 +       master->num_chipselect = 4;
 480 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 481 +       master->dev.of_node = pdev->dev.of_node;
 482 +       master->auto_runtime_pm = true;
 483 +
 484 +       sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 485 +       if (IS_ERR(sspi->hclk)) {
 486 +               dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 487 +               ret = PTR_ERR(sspi->hclk);
 488 +               goto err_free_master;
 489 +       }
 490 +
 491 +       sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 492 +       if (IS_ERR(sspi->mclk)) {
 493 +               dev_err(&pdev->dev, "Unable to acquire module clock\n");
 494 +               ret = PTR_ERR(sspi->mclk);
 495 +               goto err_free_master;
 496 +       }
 497 +
 498 +       init_completion(&sspi->done);
 499 +
 500 +       sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
 501 +       if (IS_ERR(sspi->rstc)) {
 502 +               dev_err(&pdev->dev, "Couldn't get reset controller\n");
 503 +               ret = PTR_ERR(sspi->rstc);
 504 +               goto err_free_master;
 505 +       }
 506 +
 507 +       /*
 508 +        * This wake-up/shutdown pattern is to be able to have the
 509 +        * device woken up, even if runtime_pm is disabled
 510 +        */
 511 +       ret = sun6i_spi_runtime_resume(&pdev->dev);
 512 +       if (ret) {
 513 +               dev_err(&pdev->dev, "Couldn't resume the device\n");
 514 +               goto err_free_master;
 515 +       }
 516 +
 517 +       pm_runtime_set_active(&pdev->dev);
 518 +       pm_runtime_enable(&pdev->dev);
 519 +       pm_runtime_idle(&pdev->dev);
 520 +
 521 +       ret = devm_spi_register_master(&pdev->dev, master);
 522 +       if (ret) {
 523 +               dev_err(&pdev->dev, "cannot register SPI master\n");
 524 +               goto err_pm_disable;
 525 +       }
 526 +
 527 +       return 0;
 528 +
 529 +err_pm_disable:
 530 +       pm_runtime_disable(&pdev->dev);
 531 +       sun6i_spi_runtime_suspend(&pdev->dev);
 532 +err_free_master:
 533 +       spi_master_put(master);
 534 +       return ret;
 535 +}
 536 +
 537 +static int sun6i_spi_remove(struct platform_device *pdev)
 538 +{
 539 +       pm_runtime_disable(&pdev->dev);
 540 +
 541 +       return 0;
 542 +}
 543 +
 544 +static const struct of_device_id sun6i_spi_match[] = {
 545 +       { .compatible = "allwinner,sun6i-a31-spi", },
 546 +       {}
 547 +};
 548 +MODULE_DEVICE_TABLE(of, sun6i_spi_match);
 549 +
 550 +static const struct dev_pm_ops sun6i_spi_pm_ops = {
 551 +       .runtime_resume         = sun6i_spi_runtime_resume,
 552 +       .runtime_suspend        = sun6i_spi_runtime_suspend,
 553 +};
 554 +
 555 +static struct platform_driver sun6i_spi_driver = {
 556 +       .probe  = sun6i_spi_probe,
 557 +       .remove = sun6i_spi_remove,
 558 +       .driver = {
 559 +               .name           = "sun6i-spi",
 560 +               .owner          = THIS_MODULE,
 561 +               .of_match_table = sun6i_spi_match,
 562 +               .pm             = &sun6i_spi_pm_ops,
 563 +       },
 564 +};
 565 +module_platform_driver(sun6i_spi_driver);
 566 +
 567 +MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
 568 +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 569 +MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
 570 +MODULE_LICENSE("GPL");
 571 --
 572 1.8.5.5
 573
 574
 575 From 7961656a6f11b69966500d7bd25273203fd930da Mon Sep 17 00:00:00 2001
 576 From: Mark Brown <broonie@linaro.org>
 577 Date: Thu, 6 Feb 2014 10:53:51 +0000
 578 Subject: [PATCH 2/2] spi/sunxi: Add missing dependency on RESET_CONTROLLER
 579
 580 Signed-off-by: Mark Brown <broonie@linaro.org>
 581 ---
 582  drivers/spi/Kconfig | 1 +
 583  1 file changed, 1 insertion(+)
 584
 585 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
 586 index 7cfe0ee..0ec4641 100644
 587 --- a/drivers/spi/Kconfig
 588 +++ b/drivers/spi/Kconfig
 589 @@ -449,6 +449,7 @@ config SPI_SIRF
 590  config SPI_SUN6I
 591         tristate "Allwinner A31 SPI controller"
 592         depends on ARCH_SUNXI || COMPILE_TEST
 593 +       depends on RESET_CONTROLLER
 594         help
 595           This enables using the SPI controller on the Allwinner A31 SoCs.
 596
 597 --
 598 1.8.5.5
 599