target/linux/sunxi/patches-3.13/119-dt-sunxi-add-pll5-pll6.patch

   1 From 6d3ca59232090bff1b5e1abfd3417a3859e47425 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:38 -0300
   4 Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
  10 device trees.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 ---
  15  arch/arm/boot/dts/sun4i-a10.dtsi  | 19 +++++++++++++++++--
  16  arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
  17  arch/arm/boot/dts/sun5i-a13.dtsi  | 19 +++++++++++++++++--
  18  arch/arm/boot/dts/sun7i-a20.dtsi  | 28 ++++++++++++++++------------
  19  4 files changed, 67 insertions(+), 18 deletions(-)
  20
  21 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  22 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  23 @@ -73,6 +73,22 @@
  24                         clocks = <&osc24M>;
  25                 };
  26
  27 +               pll5: pll5@01c20020 {
  28 +                       #clock-cells = <1>;
  29 +                       compatible = "allwinner,sun4i-pll5-clk";
  30 +                       reg = <0x01c20020 0x4>;
  31 +                       clocks = <&osc24M>;
  32 +                       clock-output-names = "pll5_ddr", "pll5_other";
  33 +               };
  34 +
  35 +               pll6: pll6@01c20028 {
  36 +                       #clock-cells = <1>;
  37 +                       compatible = "allwinner,sun4i-pll6-clk";
  38 +                       reg = <0x01c20028 0x4>;
  39 +                       clocks = <&osc24M>;
  40 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
  41 +               };
  42 +
  43                 /* dummy is 200M */
  44                 cpu: cpu@01c20054 {
  45                         #clock-cells = <0>;
  46 @@ -138,12 +154,11 @@
  47                                 "apb0_ir1", "apb0_keypad";
  48                 };
  49
  50 -               /* dummy is pll62 */
  51                 apb1_mux: apb1_mux@01c20058 {
  52                         #clock-cells = <0>;
  53                         compatible = "allwinner,sun4i-apb1-mux-clk";
  54                         reg = <0x01c20058 0x4>;
  55 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
  56 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
  57                 };
  58
  59                 apb1: apb1@01c20058 {
  60 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  61 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  62 @@ -70,6 +70,22 @@
  63                         clocks = <&osc24M>;
  64                 };
  65
  66 +               pll5: pll5@01c20020 {
  67 +                       #clock-cells = <1>;
  68 +                       compatible = "allwinner,sun4i-pll5-clk";
  69 +                       reg = <0x01c20020 0x4>;
  70 +                       clocks = <&osc24M>;
  71 +                       clock-output-names = "pll5_ddr", "pll5_other";
  72 +               };
  73 +
  74 +               pll6: pll6@01c20028 {
  75 +                       #clock-cells = <1>;
  76 +                       compatible = "allwinner,sun4i-pll6-clk";
  77 +                       reg = <0x01c20028 0x4>;
  78 +                       clocks = <&osc24M>;
  79 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
  80 +               };
  81 +
  82                 /* dummy is 200M */
  83                 cpu: cpu@01c20054 {
  84                         #clock-cells = <0>;
  85 @@ -130,12 +146,11 @@
  86                                 "apb0_ir", "apb0_keypad";
  87                 };
  88
  89 -               /* dummy is pll62 */
  90                 apb1_mux: apb1_mux@01c20058 {
  91                         #clock-cells = <0>;
  92                         compatible = "allwinner,sun4i-apb1-mux-clk";
  93                         reg = <0x01c20058 0x4>;
  94 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
  95 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
  96                 };
  97
  98                 apb1: apb1@01c20058 {
  99 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 100 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 101 @@ -74,6 +74,22 @@
 102                         clocks = <&osc24M>;
 103                 };
 104
 105 +               pll5: pll5@01c20020 {
 106 +                       #clock-cells = <1>;
 107 +                       compatible = "allwinner,sun4i-pll5-clk";
 108 +                       reg = <0x01c20020 0x4>;
 109 +                       clocks = <&osc24M>;
 110 +                       clock-output-names = "pll5_ddr", "pll5_other";
 111 +               };
 112 +
 113 +               pll6: pll6@01c20028 {
 114 +                       #clock-cells = <1>;
 115 +                       compatible = "allwinner,sun4i-pll6-clk";
 116 +                       reg = <0x01c20028 0x4>;
 117 +                       clocks = <&osc24M>;
 118 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
 119 +               };
 120 +
 121                 /* dummy is 200M */
 122                 cpu: cpu@01c20054 {
 123                         #clock-cells = <0>;
 124 @@ -132,12 +148,11 @@
 125                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 126                 };
 127
 128 -               /* dummy is pll6 */
 129                 apb1_mux: apb1_mux@01c20058 {
 130                         #clock-cells = <0>;
 131                         compatible = "allwinner,sun4i-apb1-mux-clk";
 132                         reg = <0x01c20058 0x4>;
 133 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
 134 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 135                 };
 136
 137                 apb1: apb1@01c20058 {
 138 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
 139 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
 140 @@ -69,23 +69,27 @@
 141                         clocks = <&osc24M>;
 142                 };
 143
 144 -               /*
 145 -                * This is a dummy clock, to be used as placeholder on
 146 -                * other mux clocks when a specific parent clock is not
 147 -                * yet implemented. It should be dropped when the driver
 148 -                * is complete.
 149 -                */
 150 -               pll6: pll6 {
 151 -                       #clock-cells = <0>;
 152 -                       compatible = "fixed-clock";
 153 -                       clock-frequency = <0>;
 154 +               pll5: pll5@01c20020 {
 155 +                       #clock-cells = <1>;
 156 +                       compatible = "allwinner,sun4i-pll5-clk";
 157 +                       reg = <0x01c20020 0x4>;
 158 +                       clocks = <&osc24M>;
 159 +                       clock-output-names = "pll5_ddr", "pll5_other";
 160 +               };
 161 +
 162 +               pll6: pll6@01c20028 {
 163 +                       #clock-cells = <1>;
 164 +                       compatible = "allwinner,sun4i-pll6-clk";
 165 +                       reg = <0x01c20028 0x4>;
 166 +                       clocks = <&osc24M>;
 167 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
 168                 };
 169
 170                 cpu: cpu@01c20054 {
 171                         #clock-cells = <0>;
 172                         compatible = "allwinner,sun4i-cpu-clk";
 173                         reg = <0x01c20054 0x4>;
 174 -                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
 175 +                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 176                 };
 177
 178                 axi: axi@01c20054 {
 179 @@ -144,7 +148,7 @@
 180                         #clock-cells = <0>;
 181                         compatible = "allwinner,sun4i-apb1-mux-clk";
 182                         reg = <0x01c20058 0x4>;
 183 -                       clocks = <&osc24M>, <&pll6>, <&osc32k>;
 184 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 185                 };
 186
 187                 apb1: apb1@01c20058 {