target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2005 Wu Qi Ming infineon
  17  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/module.h>
  26
  27 #include <asm/bootinfo.h>
  28 #include <asm/irq.h>
  29 #include <asm/ifxmips/ifxmips.h>
  30 #include <asm/ifxmips/ifxmips_irq.h>
  31 #include <asm/irq_cpu.h>
  32
  33 void ifxmips_disable_irq(unsigned int irq_nr)
  34 {
  35         int i;
  36         u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
  37
  38         irq_nr -= INT_NUM_IRQ0;
  39         for (i = 0; i <= 4; i++) {
  40                 if (irq_nr < INT_NUM_IM_OFFSET) {
  41                         ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr),
  42                                 ifxmips_ier);
  43                         return;
  44                 }
  45                 ifxmips_ier += IFXMIPS_ICU_OFFSET;
  46                 irq_nr -= INT_NUM_IM_OFFSET;
  47         }
  48 }
  49 EXPORT_SYMBOL(ifxmips_disable_irq);
  50
  51 void ifxmips_mask_and_ack_irq(unsigned int irq_nr)
  52 {
  53         int i;
  54         u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
  55         u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR;
  56
  57         irq_nr -= INT_NUM_IRQ0;
  58         for (i = 0; i <= 4; i++) {
  59                 if (irq_nr < INT_NUM_IM_OFFSET) {
  60                         ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr),
  61                                 ifxmips_ier);
  62                         ifxmips_w32((1 << irq_nr), ifxmips_isr);
  63                         return;
  64                 }
  65                 ifxmips_ier += IFXMIPS_ICU_OFFSET;
  66                 ifxmips_isr += IFXMIPS_ICU_OFFSET;
  67                 irq_nr -= INT_NUM_IM_OFFSET;
  68         }
  69 }
  70 EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
  71
  72 void ifxmips_enable_irq(unsigned int irq_nr)
  73 {
  74         int i;
  75         u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
  76
  77         irq_nr -= INT_NUM_IRQ0;
  78         for (i = 0; i <= 4; i++) {
  79                 if (irq_nr < INT_NUM_IM_OFFSET) {
  80                         ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr),
  81                                 ifxmips_ier);
  82                         return;
  83                 }
  84                 ifxmips_ier += IFXMIPS_ICU_OFFSET;
  85                 irq_nr -= INT_NUM_IM_OFFSET;
  86         }
  87 }
  88 EXPORT_SYMBOL(ifxmips_enable_irq);
  89
  90 static unsigned int ifxmips_startup_irq(unsigned int irq)
  91 {
  92         ifxmips_enable_irq(irq);
  93         return 0;
  94 }
  95
  96 static void ifxmips_end_irq(unsigned int irq)
  97 {
  98         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  99                 ifxmips_enable_irq(irq);
 100 }
 101
 102 static struct hw_interrupt_type ifxmips_irq_type = {
 103         "IFXMIPS",
 104         .startup = ifxmips_startup_irq,
 105         .enable = ifxmips_enable_irq,
 106         .disable = ifxmips_disable_irq,
 107         .unmask = ifxmips_enable_irq,
 108         .ack = ifxmips_end_irq,
 109         .mask = ifxmips_disable_irq,
 110         .mask_ack = ifxmips_mask_and_ack_irq,
 111         .end = ifxmips_end_irq,
 112 };
 113
 114 static inline int ls1bit32(unsigned long x)
 115 {
 116         __asm__ (
 117                 ".set push \n"
 118                 ".set mips32 \n"
 119                 "clz %0, %1 \n"
 120                 ".set pop \n"
 121                 : "=r" (x)
 122                 : "r" (x));
 123         return 31 - x;
 124 }
 125
 126 void ifxmips_hw_irqdispatch(int module)
 127 {
 128         u32 irq;
 129
 130         irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
 131         if (irq == 0)
 132                 return;
 133
 134         /* we need to do this due to a silicon bug */
 135         irq = ls1bit32(irq);
 136         do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 137
 138         if ((irq == 22) && (module == 0))
 139                 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
 140                         IFXMIPS_EBU_PCC_ISTAT);
 141 }
 142
 143 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
 144 #define DEFINE_HWx_IRQDISPATCH(x) \
 145 static void ifxmips_hw ## x ## _irqdispatch(void)\
 146 {\
 147         ifxmips_hw_irqdispatch(x); \
 148 }
 149 static void ifxmips_hw5_irqdispatch(void)
 150 {
 151         do_IRQ(MIPS_CPU_TIMER_IRQ);
 152 }
 153 DEFINE_HWx_IRQDISPATCH(0)
 154 DEFINE_HWx_IRQDISPATCH(1)
 155 DEFINE_HWx_IRQDISPATCH(2)
 156 DEFINE_HWx_IRQDISPATCH(3)
 157 DEFINE_HWx_IRQDISPATCH(4)
 158 /*DEFINE_HWx_IRQDISPATCH(5)*/
 159 #endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
 160
 161 asmlinkage void plat_irq_dispatch(void)
 162 {
 163         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 164         unsigned int i;
 165
 166         if (pending & CAUSEF_IP7) {
 167                 do_IRQ(MIPS_CPU_TIMER_IRQ);
 168                 goto out;
 169         } else {
 170                 for (i = 0; i < 5; i++) {
 171                         if (pending & (CAUSEF_IP2 << i)) {
 172                                 ifxmips_hw_irqdispatch(i);
 173                                 goto out;
 174                         }
 175                 }
 176         }
 177         printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 178
 179 out:
 180         return;
 181 }
 182
 183 static struct irqaction cascade = {
 184         .handler = no_action,
 185         .flags = IRQF_DISABLED,
 186         .name = "cascade",
 187 };
 188
 189 void __init arch_init_irq(void)
 190 {
 191         int i;
 192
 193         for (i = 0; i < 5; i++)
 194                 ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
 195
 196         mips_cpu_irq_init();
 197
 198         for (i = 2; i <= 6; i++)
 199                 setup_irq(i, &cascade);
 200
 201 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
 202         if (cpu_has_vint) {
 203                 printk(KERN_INFO "Setting up vectored interrupts\n");
 204                 set_vi_handler(2, ifxmips_hw0_irqdispatch);
 205                 set_vi_handler(3, ifxmips_hw1_irqdispatch);
 206                 set_vi_handler(4, ifxmips_hw2_irqdispatch);
 207                 set_vi_handler(5, ifxmips_hw3_irqdispatch);
 208                 set_vi_handler(6, ifxmips_hw4_irqdispatch);
 209                 set_vi_handler(7, ifxmips_hw5_irqdispatch);
 210         }
 211 #endif /* CONFIG_CPU_MIPSR2_IRQ_VI */
 212
 213         for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET));
 214                 i++)
 215                 set_irq_chip_and_handler(i, &ifxmips_irq_type,
 216                         handle_level_irq);
 217
 218         #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
 219         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
 220                 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 221         #else
 222         set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
 223                 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 224         #endif
 225 }
 226
 227 void __cpuinit arch_fixup_c0_irqs(void)
 228 {
 229         /* FIXME: check for CPUID and only do fix for specific chips/versions */
 230         cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
 231         cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
 232 }