2 * rtl8306.c: RTL8306S switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <net/genetlink.h>
25 #include <linux/switch.h>
26 #include <linux/delay.h>
27 #include <linux/phy.h>
32 #define RTL8306_REG_PAGE 16
33 #define RTL8306_REG_PAGE_LO (1 << 15)
34 #define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
36 #define RTL8306_NUM_VLANS 16
37 #define RTL8306_NUM_PORTS 6
38 #define RTL8306_PORT_CPU 5
39 #define RTL8306_NUM_PAGES 4
40 #define RTL8306_NUM_REGS 32
42 #define RTL_NAME_S "RTL8306S"
43 #define RTL_NAME_SD "RTL8306SD"
44 #define RTL_NAME_SDM "RTL8306SDM"
45 #define RTL_NAME_UNKNOWN "RTL8306(unknown)"
47 #define RTL8306_MAGIC 0x8306
49 static LIST_HEAD(phydevs);
52 struct list_head list;
53 struct switch_dev dev;
58 char hwname[sizeof(RTL_NAME_UNKNOWN)];
67 #define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev)
84 #define RTL_VLAN_REGOFS(name) \
85 (RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name)
87 #define RTL_PORT_REGOFS(name) \
88 (RTL_REG_PORT1_##name - RTL_REG_PORT0_##name)
90 #define RTL_PORT_REG(id, reg) \
91 (RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg)))
93 #define RTL_VLAN_REG(id, reg) \
94 (RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg)))
96 #define RTL_GLOBAL_REGATTR(reg) \
97 .id = RTL_REG_##reg, \
98 .type = SWITCH_TYPE_INT, \
100 .set = rtl_attr_set_int, \
101 .get = rtl_attr_get_int
103 #define RTL_PORT_REGATTR(reg) \
104 .id = RTL_REG_PORT0_##reg, \
105 .type = SWITCH_TYPE_INT, \
106 .ofs = RTL_PORT_REGOFS(reg), \
107 .set = rtl_attr_set_port_int, \
108 .get = rtl_attr_get_port_int
110 #define RTL_VLAN_REGATTR(reg) \
111 .id = RTL_REG_VLAN0_##reg, \
112 .type = SWITCH_TYPE_INT, \
113 .ofs = RTL_VLAN_REGOFS(reg), \
114 .set = rtl_attr_set_vlan_int, \
115 .get = rtl_attr_get_vlan_int
128 RTL_REG_TRUNK_PORTSEL,
134 RTL_REG_VLAN_TAG_ONLY,
135 RTL_REG_VLAN_TAG_AWARE,
136 #define RTL_VLAN_ENUM(id) \
137 RTL_REG_VLAN##id##_VID, \
138 RTL_REG_VLAN##id##_PORTMASK
155 #define RTL_PORT_ENUM(id) \
156 RTL_REG_PORT##id##_PVID, \
157 RTL_REG_PORT##id##_NULL_VID_REPLACE, \
158 RTL_REG_PORT##id##_NON_PVID_DISCARD, \
159 RTL_REG_PORT##id##_VID_INSERT, \
160 RTL_REG_PORT##id##_TAG_INSERT, \
161 RTL_REG_PORT##id##_LINK, \
162 RTL_REG_PORT##id##_SPEED, \
163 RTL_REG_PORT##id##_NWAY, \
164 RTL_REG_PORT##id##_NRESTART, \
165 RTL_REG_PORT##id##_DUPLEX, \
166 RTL_REG_PORT##id##_RXEN, \
167 RTL_REG_PORT##id##_TXEN
176 static const struct rtl_reg rtl_regs[] = {
177 [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 },
178 [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 },
179 [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 },
181 /* CPU port number */
182 [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 },
183 /* Enable CPU port function */
184 [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 },
185 /* Enable CPU port tag insertion */
186 [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 },
187 /* Enable CPU port tag removal */
188 [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 },
189 /* Enable CPU port tag checking */
190 [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 },
191 [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 },
192 [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 },
193 [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 },
195 [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 },
197 [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 },
198 [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 },
199 [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 },
200 [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 },
202 #define RTL_VLAN_REGS(id, phy, page, regofs) \
203 [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
204 [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
205 RTL_VLAN_REGS( 0, 0, 0, 0),
206 RTL_VLAN_REGS( 1, 1, 0, 0),
207 RTL_VLAN_REGS( 2, 2, 0, 0),
208 RTL_VLAN_REGS( 3, 3, 0, 0),
209 RTL_VLAN_REGS( 4, 4, 0, 0),
210 RTL_VLAN_REGS( 5, 0, 1, 2),
211 RTL_VLAN_REGS( 6, 1, 1, 2),
212 RTL_VLAN_REGS( 7, 2, 1, 2),
213 RTL_VLAN_REGS( 8, 3, 1, 2),
214 RTL_VLAN_REGS( 9, 4, 1, 2),
215 RTL_VLAN_REGS(10, 0, 1, 4),
216 RTL_VLAN_REGS(11, 1, 1, 4),
217 RTL_VLAN_REGS(12, 2, 1, 4),
218 RTL_VLAN_REGS(13, 3, 1, 4),
219 RTL_VLAN_REGS(14, 4, 1, 4),
220 RTL_VLAN_REGS(15, 0, 1, 6),
222 #define REG_PORT_SETTING(port, phy) \
223 [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
224 [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
225 [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
226 [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
227 [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
228 [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
229 [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
230 [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
231 [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
232 [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
233 [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
235 REG_PORT_SETTING(0, 0),
236 REG_PORT_SETTING(1, 1),
237 REG_PORT_SETTING(2, 2),
238 REG_PORT_SETTING(3, 3),
239 REG_PORT_SETTING(4, 4),
240 REG_PORT_SETTING(5, 6),
242 #define REG_PORT_PVID(phy, page, regofs) \
243 { page, phy, 24 + regofs, 4, 12, 0 }
244 [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),
245 [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),
246 [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),
247 [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),
248 [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),
249 [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),
254 rtl_set_page(struct rtl_priv *priv, unsigned int page)
256 struct mii_bus *bus = priv->bus;
259 if (priv->page == page)
262 BUG_ON(page > RTL8306_NUM_PAGES);
263 pgsel = bus->read(bus, 0, RTL8306_REG_PAGE);
264 pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);
266 pgsel |= RTL8306_REG_PAGE_LO;
267 if (!(page & (1 << 1))) /* bit is inverted */
268 pgsel |= RTL8306_REG_PAGE_HI;
269 bus->write(bus, 0, RTL8306_REG_PAGE, pgsel);
273 rtl_w16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 val)
275 struct rtl_priv *priv = to_rtl(dev);
276 struct mii_bus *bus = priv->bus;
278 rtl_set_page(priv, page);
279 bus->write(bus, phy, reg, val);
280 bus->read(bus, phy, reg); /* flush */
285 rtl_r16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg)
287 struct rtl_priv *priv = to_rtl(dev);
288 struct mii_bus *bus = priv->bus;
290 rtl_set_page(priv, page);
291 return bus->read(bus, phy, reg);
295 rtl_rmw(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 mask, u16 val)
297 struct rtl_priv *priv = to_rtl(dev);
298 struct mii_bus *bus = priv->bus;
301 rtl_set_page(priv, page);
302 r = bus->read(bus, phy, reg);
305 bus->write(bus, phy, reg, r);
306 return bus->read(bus, phy, reg); /* flush */
311 rtl_get(struct switch_dev *dev, enum rtl_regidx s)
313 const struct rtl_reg *r = &rtl_regs[s];
316 BUG_ON(s >= ARRAY_SIZE(rtl_regs));
317 if (r->bits == 0) /* unimplemented */
320 val = rtl_r16(dev, r->page, r->phy, r->reg);
328 val &= (1 << r->bits) - 1;
334 rtl_set(struct switch_dev *dev, enum rtl_regidx s, unsigned int val)
336 const struct rtl_reg *r = &rtl_regs[s];
339 BUG_ON(s >= ARRAY_SIZE(rtl_regs));
341 if (r->bits == 0) /* unimplemented */
351 mask = (1 << r->bits) - 1;
355 return rtl_rmw(dev, r->page, r->phy, r->reg, mask, val);
359 rtl_phy_save(struct switch_dev *dev, int port, struct rtl_phyregs *regs)
361 regs->nway = rtl_get(dev, RTL_PORT_REG(port, NWAY));
362 regs->speed = rtl_get(dev, RTL_PORT_REG(port, SPEED));
363 regs->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX));
367 rtl_phy_restore(struct switch_dev *dev, int port, struct rtl_phyregs *regs)
369 rtl_set(dev, RTL_PORT_REG(port, NWAY), regs->nway);
370 rtl_set(dev, RTL_PORT_REG(port, SPEED), regs->speed);
371 rtl_set(dev, RTL_PORT_REG(port, DUPLEX), regs->duplex);
375 rtl_port_set_enable(struct switch_dev *dev, int port, int enabled)
377 rtl_set(dev, RTL_PORT_REG(port, RXEN), enabled);
378 rtl_set(dev, RTL_PORT_REG(port, TXEN), enabled);
380 if ((port >= 5) || !enabled)
383 /* restart autonegotiation if enabled */
384 rtl_set(dev, RTL_PORT_REG(port, NRESTART), 1);
388 rtl_hw_apply(struct switch_dev *dev)
391 int trunk_en, trunk_psel;
392 struct rtl_phyregs port5;
394 rtl_phy_save(dev, 5, &port5);
396 /* disable rx/tx from PHYs */
397 for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
398 rtl_port_set_enable(dev, i, 0);
401 /* save trunking status */
402 trunk_en = rtl_get(dev, RTL_REG_EN_TRUNK);
403 trunk_psel = rtl_get(dev, RTL_REG_TRUNK_PORTSEL);
405 /* trunk port 3 and 4
406 * XXX: Big WTF, but RealTek seems to do it */
407 rtl_set(dev, RTL_REG_EN_TRUNK, 1);
408 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 1);
410 /* execute the software reset */
411 rtl_set(dev, RTL_REG_RESET, 1);
413 /* wait for the reset to complete,
414 * but don't wait for too long */
415 for (i = 0; i < 10; i++) {
416 if (rtl_get(dev, RTL_REG_RESET) == 0)
422 /* enable rx/tx from PHYs */
423 for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
424 rtl_port_set_enable(dev, i, 1);
427 /* restore trunking settings */
428 rtl_set(dev, RTL_REG_EN_TRUNK, trunk_en);
429 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, trunk_psel);
430 rtl_phy_restore(dev, 5, &port5);
436 rtl_hw_init(struct switch_dev *dev)
438 struct rtl_priv *priv = to_rtl(dev);
439 int cpu_mask = 1 << dev->cpu_port;
442 rtl_set(dev, RTL_REG_VLAN_ENABLE, 0);
443 rtl_set(dev, RTL_REG_VLAN_FILTER, 0);
444 rtl_set(dev, RTL_REG_EN_TRUNK, 0);
445 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 0);
447 /* initialize cpu port settings */
449 rtl_set(dev, RTL_REG_CPUPORT, dev->cpu_port);
450 rtl_set(dev, RTL_REG_EN_CPUPORT, 1);
452 rtl_set(dev, RTL_REG_CPUPORT, 7);
453 rtl_set(dev, RTL_REG_EN_CPUPORT, 0);
455 rtl_set(dev, RTL_REG_EN_TAG_OUT, 0);
456 rtl_set(dev, RTL_REG_EN_TAG_IN, 0);
457 rtl_set(dev, RTL_REG_EN_TAG_CLR, 0);
459 /* reset all vlans */
460 for (i = 0; i < RTL8306_NUM_VLANS; i++) {
461 rtl_set(dev, RTL_VLAN_REG(i, VID), i);
462 rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), 0);
465 /* default to port isolation */
466 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
469 if ((1 << i) == cpu_mask)
470 mask = ((1 << RTL8306_NUM_PORTS) - 1) & ~cpu_mask; /* all bits set */
472 mask = cpu_mask | (1 << i);
474 rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), mask);
475 rtl_set(dev, RTL_PORT_REG(i, PVID), i);
476 rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
477 rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), 1);
478 rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), 3);
485 rtl_set_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
487 struct rtl_priv *priv = to_rtl(dev);
488 priv->do_cpu = val->value.i;
494 rtl_get_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
496 struct rtl_priv *priv = to_rtl(dev);
497 val->value.i = priv->do_cpu;
502 rtl_set_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
504 dev->cpu_port = val->value.i;
510 rtl_get_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
512 val->value.i = dev->cpu_port;
518 rtl_reset(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
525 rtl_attr_set_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
527 int idx = attr->id + (val->port_vlan * attr->ofs);
528 struct rtl_phyregs port;
530 if (attr->id >= ARRAY_SIZE(rtl_regs))
533 if ((attr->max > 0) && (val->value.i > attr->max))
536 /* access to phy register 22 on port 4/5
537 * needs phy status save/restore */
538 if ((val->port_vlan > 3) &&
539 (rtl_regs[idx].reg == 22) &&
540 (rtl_regs[idx].page == 0)) {
542 rtl_phy_save(dev, val->port_vlan, &port);
543 rtl_set(dev, idx, val->value.i);
544 rtl_phy_restore(dev, val->port_vlan, &port);
546 rtl_set(dev, idx, val->value.i);
553 rtl_attr_get_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
555 int idx = attr->id + (val->port_vlan * attr->ofs);
557 if (idx >= ARRAY_SIZE(rtl_regs))
560 val->value.i = rtl_get(dev, idx);
565 rtl_attr_set_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
567 if (val->port_vlan >= RTL8306_NUM_PORTS)
570 return rtl_attr_set_int(dev, attr, val);
574 rtl_attr_get_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
576 if (val->port_vlan >= RTL8306_NUM_PORTS)
578 return rtl_attr_get_int(dev, attr, val);
582 rtl_attr_set_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
584 if (val->port_vlan >= dev->vlans)
587 return rtl_attr_set_int(dev, attr, val);
591 rtl_attr_get_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
593 if (val->port_vlan >= dev->vlans)
596 return rtl_attr_get_int(dev, attr, val);
600 rtl_get_ports(struct switch_dev *dev, struct switch_val *val)
602 unsigned int i, mask;
604 mask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));
605 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
606 struct switch_port *port;
608 if (!(mask & (1 << i)))
611 port = &val->value.ports[val->len];
621 rtl_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
623 struct rtl_priv *priv = to_rtl(dev);
624 struct rtl_phyregs port;
625 int en = val->value.i;
628 rtl_set(dev, RTL_REG_EN_TAG_OUT, en && priv->do_cpu);
629 rtl_set(dev, RTL_REG_EN_TAG_IN, en && priv->do_cpu);
630 rtl_set(dev, RTL_REG_EN_TAG_CLR, en && priv->do_cpu);
631 rtl_set(dev, RTL_REG_VLAN_TAG_AWARE, en);
633 rtl_set(dev, RTL_REG_VLAN_FILTER, en);
635 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
637 rtl_phy_save(dev, val->port_vlan, &port);
638 rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
639 rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), (en ? (i == dev->cpu_port ? 0 : 1) : 1));
640 rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), (en ? (i == dev->cpu_port ? 2 : 1) : 3));
642 rtl_phy_restore(dev, val->port_vlan, &port);
644 rtl_set(dev, RTL_REG_VLAN_ENABLE, en);
650 rtl_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
652 return rtl_get(dev, RTL_REG_VLAN_ENABLE);
656 rtl_set_ports(struct switch_dev *dev, struct switch_val *val)
658 unsigned int mask = 0;
659 unsigned int oldmask;
662 for(i = 0; i < val->len; i++)
664 struct switch_port *port = &val->value.ports[i];
667 mask |= (1 << port->id);
669 if (port->id == dev->cpu_port)
672 if ((i == dev->cpu_port) ||
673 (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)))
676 /* fix up PVIDs for added ports */
678 rtl_set(dev, RTL_PORT_REG(port->id, PVID), val->port_vlan);
680 rtl_set(dev, RTL_PORT_REG(port->id, NON_PVID_DISCARD), (tagged ? 0 : 1));
681 rtl_set(dev, RTL_PORT_REG(port->id, VID_INSERT), (tagged ? 0 : 1));
682 rtl_set(dev, RTL_PORT_REG(port->id, TAG_INSERT), (tagged ? 2 : 1));
685 oldmask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));
686 rtl_set(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK), mask);
688 /* fix up PVIDs for removed ports, default to last vlan */
690 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
691 if (!(oldmask & (1 << i)))
694 if (i == dev->cpu_port)
697 if (rtl_get(dev, RTL_PORT_REG(i, PVID)) == val->port_vlan)
698 rtl_set(dev, RTL_PORT_REG(i, PVID), dev->vlans - 1);
704 static struct switch_attr rtl_globals[] = {
706 .type = SWITCH_TYPE_INT,
708 .description = "Reset the switch",
712 .type = SWITCH_TYPE_INT,
713 .name = "enable_vlan",
714 .description = "Enable VLAN mode",
720 RTL_GLOBAL_REGATTR(EN_TRUNK),
722 .description = "Enable port trunking",
726 RTL_GLOBAL_REGATTR(TRUNK_PORTSEL),
728 .description = "Select ports for trunking (0: 0,1 - 1: 3,4)",
733 RTL_GLOBAL_REGATTR(VLAN_FILTER),
734 .name = "vlan_filter",
735 .description = "Filter incoming packets for allowed VLANS",
739 .type = SWITCH_TYPE_INT,
741 .description = "CPU Port",
742 .set = rtl_set_cpuport,
743 .get = rtl_get_cpuport,
744 .max = RTL8306_NUM_PORTS,
747 .type = SWITCH_TYPE_INT,
748 .name = "use_cpuport",
749 .description = "CPU Port handling flag",
750 .set = rtl_set_use_cpuport,
751 .get = rtl_get_use_cpuport,
752 .max = RTL8306_NUM_PORTS,
755 RTL_GLOBAL_REGATTR(TRAP_CPU),
757 .description = "VLAN trap to CPU",
761 RTL_GLOBAL_REGATTR(VLAN_TAG_AWARE),
762 .name = "vlan_tag_aware",
763 .description = "Enable VLAN tag awareness",
767 RTL_GLOBAL_REGATTR(VLAN_TAG_ONLY),
769 .description = "Only accept tagged packets",
774 static struct switch_attr rtl_port[] = {
776 RTL_PORT_REGATTR(PVID),
778 .description = "Port VLAN ID",
779 .max = RTL8306_NUM_VLANS - 1,
782 RTL_PORT_REGATTR(LINK),
784 .description = "get the current link state",
790 RTL_PORT_REGATTR(NULL_VID_REPLACE),
792 .description = "NULL VID gets replaced by port default vid",
796 RTL_PORT_REGATTR(NON_PVID_DISCARD),
797 .name = "non_pvid_discard",
798 .description = "discard packets with VID != PVID",
802 RTL_PORT_REGATTR(VID_INSERT),
803 .name = "vid_insert_remove",
804 .description = "how should the switch insert and remove vids ?",
808 RTL_PORT_REGATTR(TAG_INSERT),
809 .name = "tag_insert",
810 .description = "tag insertion handling",
815 RTL_PORT_REGATTR(SPEED),
817 .description = "current link speed",
821 RTL_PORT_REGATTR(NWAY),
823 .description = "enable autonegotiation",
828 static struct switch_attr rtl_vlan[] = {
830 RTL_VLAN_REGATTR(VID),
832 .description = "VLAN ID",
837 static const struct switch_dev_ops rtl8306_ops = {
840 .n_attr = ARRAY_SIZE(rtl_globals),
844 .n_attr = ARRAY_SIZE(rtl_port),
848 .n_attr = ARRAY_SIZE(rtl_vlan),
851 .get_vlan_ports = rtl_get_ports,
852 .set_vlan_ports = rtl_set_ports,
853 .apply_config = rtl_hw_apply,
857 rtl8306_config_init(struct phy_device *pdev)
859 struct net_device *netdev = pdev->attached_dev;
860 struct rtl_priv *priv = pdev->priv;
861 struct switch_dev *dev = &priv->dev;
862 struct switch_val val;
863 unsigned int chipid, chipver, chiptype;
866 /* Only init the switch for the primary PHY */
871 priv->dev.cpu_port = RTL8306_PORT_CPU;
872 priv->dev.ports = RTL8306_NUM_PORTS;
873 priv->dev.vlans = RTL8306_NUM_VLANS;
874 priv->dev.ops = &rtl8306_ops;
877 priv->bus = pdev->bus;
879 chipid = rtl_get(dev, RTL_REG_CHIPID);
880 chipver = rtl_get(dev, RTL_REG_CHIPVER);
881 chiptype = rtl_get(dev, RTL_REG_CHIPTYPE);
885 strncpy(priv->hwname, RTL_NAME_S, sizeof(priv->hwname));
886 priv->type = RTL_TYPE_S;
889 strncpy(priv->hwname, RTL_NAME_SD, sizeof(priv->hwname));
890 priv->type = RTL_TYPE_SD;
893 strncpy(priv->hwname, RTL_NAME_SDM, sizeof(priv->hwname));
894 priv->type = RTL_TYPE_SDM;
897 strncpy(priv->hwname, RTL_NAME_UNKNOWN, sizeof(priv->hwname));
901 dev->name = priv->hwname;
904 printk(KERN_INFO "Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\n", priv->hwname, chipid, chipver);
906 err = register_switch(dev, netdev);
917 rtl8306_fixup(struct phy_device *pdev)
919 struct rtl_priv priv;
922 /* Attach to primary LAN port and WAN port */
923 if (pdev->addr != 0 && pdev->addr != 4)
927 priv.bus = pdev->bus;
928 chipid = rtl_get(&priv.dev, RTL_REG_CHIPID);
929 if (chipid == 0x5988)
930 pdev->phy_id = RTL8306_MAGIC;
936 rtl8306_probe(struct phy_device *pdev)
938 struct rtl_priv *priv;
940 list_for_each_entry(priv, &phydevs, list) {
942 * share one rtl_priv instance between virtual phy
943 * devices on the same bus
945 if (priv->bus == pdev->bus)
948 priv = kzalloc(sizeof(struct rtl_priv), GFP_KERNEL);
952 priv->bus = pdev->bus;
960 rtl8306_remove(struct phy_device *pdev)
962 struct rtl_priv *priv = pdev->priv;
963 unregister_switch(&priv->dev);
968 rtl8306_config_aneg(struct phy_device *pdev)
970 struct rtl_priv *priv = pdev->priv;
976 /* Restart autonegotiation */
977 rtl_set(&priv->dev, RTL_PORT_REG(4, NWAY), 1);
978 rtl_set(&priv->dev, RTL_PORT_REG(4, NRESTART), 1);
984 rtl8306_read_status(struct phy_device *pdev)
986 struct rtl_priv *priv = pdev->priv;
987 struct switch_dev *dev = &priv->dev;
989 if (pdev->addr == 4) {
991 pdev->speed = rtl_get(dev, RTL_PORT_REG(4, SPEED)) ? SPEED_100 : SPEED_10;
992 pdev->duplex = rtl_get(dev, RTL_PORT_REG(4, DUPLEX)) ? DUPLEX_FULL : DUPLEX_HALF;
993 pdev->link = !!rtl_get(dev, RTL_PORT_REG(4, LINK));
996 pdev->speed = SPEED_100;
997 pdev->duplex = DUPLEX_FULL;
1002 * Bypass generic PHY status read,
1003 * it doesn't work with this switch
1006 pdev->state = PHY_RUNNING;
1007 netif_carrier_on(pdev->attached_dev);
1008 pdev->adjust_link(pdev->attached_dev);
1010 pdev->state = PHY_NOLINK;
1011 netif_carrier_off(pdev->attached_dev);
1012 pdev->adjust_link(pdev->attached_dev);
1019 static struct phy_driver rtl8306_driver = {
1020 .name = "Realtek RTL8306S",
1021 .flags = PHY_HAS_MAGICANEG,
1022 .phy_id = RTL8306_MAGIC,
1023 .phy_id_mask = 0xffffffff,
1024 .features = PHY_BASIC_FEATURES,
1025 .probe = &rtl8306_probe,
1026 .remove = &rtl8306_remove,
1027 .config_init = &rtl8306_config_init,
1028 .config_aneg = &rtl8306_config_aneg,
1029 .read_status = &rtl8306_read_status,
1030 .driver = { .owner = THIS_MODULE,},
1037 phy_register_fixup_for_id(PHY_ANY_ID, rtl8306_fixup);
1038 return phy_driver_register(&rtl8306_driver);
1044 phy_driver_unregister(&rtl8306_driver);
1047 module_init(rtl_init);
1048 module_exit(rtl_exit);
1049 MODULE_LICENSE("GPL");