target/linux/atheros/files/arch/mips/atheros/ar5312/irq.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/string.h>
  20 #include <linux/kernel.h>
  21 #include <linux/reboot.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/time.h>
  24 #include <asm/irq.h>
  25 #include <asm/io.h>
  26
  27 #include <ar531x.h>
  28 #include <gpio.h>
  29
  30 /*
  31  * Called when an interrupt is received, this function
  32  * determines exactly which interrupt it was, and it
  33  * invokes the appropriate handler.
  34  *
  35  * Implicitly, we also define interrupt priority by
  36  * choosing which to dispatch first.
  37  */
  38 asmlinkage void ar5312_irq_dispatch(void)
  39 {
  40         int pending = read_c0_status() & read_c0_cause();
  41
  42         if (pending & CAUSEF_IP2)
  43                 do_IRQ(AR5312_IRQ_WLAN0_INTRS);
  44         else if (pending & CAUSEF_IP3)
  45                 do_IRQ(AR5312_IRQ_ENET0_INTRS);
  46         else if (pending & CAUSEF_IP4)
  47                 do_IRQ(AR5312_IRQ_ENET1_INTRS);
  48         else if (pending & CAUSEF_IP5)
  49                 do_IRQ(AR5312_IRQ_WLAN1_INTRS);
  50         else if (pending & CAUSEF_IP6) {
  51                 unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
  52
  53                 if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
  54                         do_IRQ(AR531X_MISC_IRQ_TIMER);
  55                         (void)sysRegRead(AR531X_TIMER);
  56                 } else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
  57                         do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
  58                 else if (ar531x_misc_intrs & AR531X_ISR_GPIO)
  59                         ar5312_gpio_irq_dispatch();
  60                 else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
  61                         do_IRQ(AR531X_MISC_IRQ_UART0);
  62                 else if (ar531x_misc_intrs & AR531X_ISR_WD)
  63                         do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
  64                 else
  65                         do_IRQ(AR531X_MISC_IRQ_NONE);
  66         } else if (pending & CAUSEF_IP7) {
  67                 do_IRQ(AR531X_IRQ_CPU_CLOCK);
  68         }
  69 }
  70
  71
  72 /* Enable the specified AR531X_MISC_IRQ interrupt */
  73 static void
  74 ar5312_misc_intr_enable(unsigned int irq)
  75 {
  76         unsigned int imr;
  77
  78         imr = sysRegRead(AR531X_IMR);
  79         imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
  80         sysRegWrite(AR531X_IMR, imr);
  81         sysRegRead(AR531X_IMR); /* flush write buffer */
  82 }
  83
  84 /* Disable the specified AR531X_MISC_IRQ interrupt */
  85 static void
  86 ar5312_misc_intr_disable(unsigned int irq)
  87 {
  88         unsigned int imr;
  89
  90         imr = sysRegRead(AR531X_IMR);
  91         imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
  92         sysRegWrite(AR531X_IMR, imr);
  93         sysRegRead(AR531X_IMR); /* flush write buffer */
  94 }
  95
  96 /* Turn on the specified AR531X_MISC_IRQ interrupt */
  97 static unsigned int
  98 ar5312_misc_intr_startup(unsigned int irq)
  99 {
 100         ar5312_misc_intr_enable(irq);
 101         return 0;
 102 }
 103
 104 /* Turn off the specified AR531X_MISC_IRQ interrupt */
 105 static void
 106 ar5312_misc_intr_shutdown(unsigned int irq)
 107 {
 108         ar5312_misc_intr_disable(irq);
 109 }
 110
 111 static void
 112 ar5312_misc_intr_ack(unsigned int irq)
 113 {
 114         ar5312_misc_intr_disable(irq);
 115 }
 116
 117 static void
 118 ar5312_misc_intr_end(unsigned int irq)
 119 {
 120         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 121                 ar5312_misc_intr_enable(irq);
 122 }
 123
 124 static struct irq_chip ar5312_misc_intr_controller = {
 125         .typename       = "AR5312 misc",
 126         .startup        = ar5312_misc_intr_startup,
 127         .shutdown       = ar5312_misc_intr_shutdown,
 128         .enable         = ar5312_misc_intr_enable,
 129         .disable        = ar5312_misc_intr_disable,
 130         .ack            = ar5312_misc_intr_ack,
 131         .end            = ar5312_misc_intr_end,
 132 };
 133
 134 static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
 135 {
 136         u32 proc1 = sysRegRead(AR531X_PROC1);
 137         u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
 138         u32 dma1 = sysRegRead(AR531X_DMA1);
 139         u32 dmaAddr = sysRegRead(AR531X_DMAADDR);   /* clears error state */
 140
 141         printk("AHB interrupt: PROCADDR=0x%8.8x  PROC1=0x%8.8x  DMAADDR=0x%8.8x  DMA1=0x%8.8x\n",
 142                         procAddr, proc1, dmaAddr, dma1);
 143
 144         machine_restart("AHB error"); /* Catastrophic failure */
 145         return IRQ_HANDLED;
 146 }
 147
 148
 149 static struct irqaction ar5312_ahb_proc_interrupt  = {
 150         .handler        = ar5312_ahb_proc_handler,
 151         .flags          = IRQF_DISABLED,
 152         .name           = "ar5312_ahb_proc_interrupt",
 153 };
 154
 155
 156 static struct irqaction cascade  = {
 157         .handler        = no_action,
 158         .flags          = IRQF_DISABLED,
 159         .name           = "cascade",
 160 };
 161
 162 void __init ar5312_misc_intr_init(int irq_base)
 163 {
 164         int i;
 165
 166         for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
 167                 irq_desc[i].status = IRQ_DISABLED;
 168                 irq_desc[i].action = NULL;
 169                 irq_desc[i].depth = 1;
 170                 irq_desc[i].chip = &ar5312_misc_intr_controller;
 171         }
 172         setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
 173         setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
 174 }
 175
 176