target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_DEFAULT_MSG_ENABLE       \
  17         (NETIF_MSG_DRV                  \
  18         | NETIF_MSG_PROBE               \
  19         | NETIF_MSG_LINK                \
  20         | NETIF_MSG_TIMER               \
  21         | NETIF_MSG_IFDOWN              \
  22         | NETIF_MSG_IFUP                \
  23         | NETIF_MSG_RX_ERR              \
  24         | NETIF_MSG_TX_ERR)
  25
  26 static int ag71xx_msg_level = -1;
  27
  28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  30
  31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  32 {
  33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  34                 ag->dev->name,
  35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38
  39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  40                 ag->dev->name,
  41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  44 }
  45
  46 static void ag71xx_dump_regs(struct ag71xx *ag)
  47 {
  48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  49                 ag->dev->name,
  50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  56                 ag->dev->name,
  57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  61                 ag->dev->name,
  62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  66                 ag->dev->name,
  67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  70 }
  71
  72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  73 {
  74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  75                 ag->dev->name, label, intr,
  76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  82 }
  83
  84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  85 {
  86         kfree(ring->buf);
  87
  88         if (ring->descs_cpu)
  89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  90                                   ring->descs_cpu, ring->descs_dma);
  91 }
  92
  93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
  94 {
  95         int err;
  96         int i;
  97
  98         ring->desc_size = sizeof(struct ag71xx_desc);
  99         if (ring->desc_size % cache_line_size()) {
 100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 101                         ring, ring->desc_size,
 102                         roundup(ring->desc_size, cache_line_size()));
 103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 104         }
 105
 106         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
 107                                              &ring->descs_dma, GFP_ATOMIC);
 108         if (!ring->descs_cpu) {
 109                 err = -ENOMEM;
 110                 goto err;
 111         }
 112
 113         ring->size = size;
 114
 115         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
 116         if (!ring->buf) {
 117                 err = -ENOMEM;
 118                 goto err;
 119         }
 120
 121         for (i = 0; i < size; i++) {
 122                 int idx = i * ring->desc_size;
 123                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
 124                 DBG("ag71xx: ring %p, desc %d at %p\n",
 125                         ring, i, ring->buf[i].desc);
 126         }
 127
 128         return 0;
 129
 130 err:
 131         return err;
 132 }
 133
 134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 135 {
 136         struct ag71xx_ring *ring = &ag->tx_ring;
 137         struct net_device *dev = ag->dev;
 138
 139         while (ring->curr != ring->dirty) {
 140                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
 141
 142                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 143                         ring->buf[i].desc->ctrl = 0;
 144                         dev->stats.tx_errors++;
 145                 }
 146
 147                 if (ring->buf[i].skb)
 148                         dev_kfree_skb_any(ring->buf[i].skb);
 149
 150                 ring->buf[i].skb = NULL;
 151
 152                 ring->dirty++;
 153         }
 154
 155         /* flush descriptors */
 156         wmb();
 157
 158 }
 159
 160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 161 {
 162         struct ag71xx_ring *ring = &ag->tx_ring;
 163         int i;
 164
 165         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
 166                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 167                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
 168
 169                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 170                 ring->buf[i].skb = NULL;
 171         }
 172
 173         /* flush descriptors */
 174         wmb();
 175
 176         ring->curr = 0;
 177         ring->dirty = 0;
 178 }
 179
 180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 181 {
 182         struct ag71xx_ring *ring = &ag->rx_ring;
 183         int i;
 184
 185         if (!ring->buf)
 186                 return;
 187
 188         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
 189                 if (ring->buf[i].skb) {
 190                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
 191                                          AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 192                         kfree_skb(ring->buf[i].skb);
 193                 }
 194 }
 195
 196 static int ag71xx_rx_reserve(struct ag71xx *ag)
 197 {
 198         int reserve = 0;
 199
 200         if (ag71xx_get_pdata(ag)->is_ar724x) {
 201                 if (!ag71xx_has_ar8216(ag))
 202                         reserve = 2;
 203
 204                 if (ag->phy_dev)
 205                         reserve += 4 - (ag->phy_dev->pkt_align % 4);
 206
 207                 reserve %= 4;
 208         }
 209
 210         return reserve + AG71XX_RX_PKT_RESERVE;
 211 }
 212
 213
 214 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 215 {
 216         struct ag71xx_ring *ring = &ag->rx_ring;
 217         unsigned int reserve = ag71xx_rx_reserve(ag);
 218         unsigned int i;
 219         int ret;
 220
 221         ret = 0;
 222         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 223                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 224                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
 225
 226                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 227                         ring->buf[i].desc,
 228                         ring->buf[i].desc->next);
 229         }
 230
 231         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 232                 struct sk_buff *skb;
 233                 dma_addr_t dma_addr;
 234
 235                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
 236                 if (!skb) {
 237                         ret = -ENOMEM;
 238                         break;
 239                 }
 240
 241                 skb->dev = ag->dev;
 242                 skb_reserve(skb, reserve);
 243
 244                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 245                                           AG71XX_RX_PKT_SIZE,
 246                                           DMA_FROM_DEVICE);
 247                 ring->buf[i].skb = skb;
 248                 ring->buf[i].dma_addr = dma_addr;
 249                 ring->buf[i].desc->data = (u32) dma_addr;
 250                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 251         }
 252
 253         /* flush descriptors */
 254         wmb();
 255
 256         ring->curr = 0;
 257         ring->dirty = 0;
 258
 259         return ret;
 260 }
 261
 262 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 263 {
 264         struct ag71xx_ring *ring = &ag->rx_ring;
 265         unsigned int reserve = ag71xx_rx_reserve(ag);
 266         unsigned int count;
 267
 268         count = 0;
 269         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 270                 unsigned int i;
 271
 272                 i = ring->dirty % AG71XX_RX_RING_SIZE;
 273
 274                 if (ring->buf[i].skb == NULL) {
 275                         dma_addr_t dma_addr;
 276                         struct sk_buff *skb;
 277
 278                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
 279                         if (skb == NULL)
 280                                 break;
 281
 282                         skb_reserve(skb, reserve);
 283                         skb->dev = ag->dev;
 284
 285                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 286                                                   AG71XX_RX_PKT_SIZE,
 287                                                   DMA_FROM_DEVICE);
 288
 289                         ring->buf[i].skb = skb;
 290                         ring->buf[i].dma_addr = dma_addr;
 291                         ring->buf[i].desc->data = (u32) dma_addr;
 292                 }
 293
 294                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 295                 count++;
 296         }
 297
 298         /* flush descriptors */
 299         wmb();
 300
 301         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 302
 303         return count;
 304 }
 305
 306 static int ag71xx_rings_init(struct ag71xx *ag)
 307 {
 308         int ret;
 309
 310         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
 311         if (ret)
 312                 return ret;
 313
 314         ag71xx_ring_tx_init(ag);
 315
 316         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
 317         if (ret)
 318                 return ret;
 319
 320         ret = ag71xx_ring_rx_init(ag);
 321         return ret;
 322 }
 323
 324 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 325 {
 326         ag71xx_ring_rx_clean(ag);
 327         ag71xx_ring_free(&ag->rx_ring);
 328
 329         ag71xx_ring_tx_clean(ag);
 330         ag71xx_ring_free(&ag->tx_ring);
 331 }
 332
 333 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 334 {
 335         switch (ag->speed) {
 336         case SPEED_1000:
 337                 return "1000";
 338         case SPEED_100:
 339                 return "100";
 340         case SPEED_10:
 341                 return "10";
 342         }
 343
 344         return "?";
 345 }
 346
 347 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 348 {
 349         u32 t;
 350
 351         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
 352           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
 353
 354         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 355
 356         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
 357         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 358 }
 359
 360 static void ag71xx_dma_reset(struct ag71xx *ag)
 361 {
 362         u32 val;
 363         int i;
 364
 365         ag71xx_dump_dma_regs(ag);
 366
 367         /* stop RX and TX */
 368         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 369         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 370
 371         /*
 372          * give the hardware some time to really stop all rx/tx activity
 373          * clearing the descriptors too early causes random memory corruption
 374          */
 375         mdelay(1);
 376
 377         /* clear descriptor addresses */
 378         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
 379         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
 380
 381         /* clear pending RX/TX interrupts */
 382         for (i = 0; i < 256; i++) {
 383                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 384                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 385         }
 386
 387         /* clear pending errors */
 388         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 389         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 390
 391         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 392         if (val)
 393                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
 394                         ag->dev->name, val);
 395
 396         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 397
 398         /* mask out reserved bits */
 399         val &= ~0xff000000;
 400
 401         if (val)
 402                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
 403                         ag->dev->name, val);
 404
 405         ag71xx_dump_dma_regs(ag);
 406 }
 407
 408 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 409                          MAC_CFG1_SRX | MAC_CFG1_STX)
 410
 411 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 412
 413 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 414                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 415                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 416                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 417                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 418                          FIFO_CFG4_VT)
 419
 420 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 421                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 422                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 423                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 424                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 425                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 426
 427 static void ag71xx_hw_stop(struct ag71xx *ag)
 428 {
 429         /* disable all interrupts and stop the rx/tx engine */
 430         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 431         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 432         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 433 }
 434
 435 static void ag71xx_hw_setup(struct ag71xx *ag)
 436 {
 437         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 438
 439         /* setup MAC configuration registers */
 440         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 441
 442         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 443                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 444
 445         /* setup max frame length */
 446         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
 447
 448         /* setup MII interface type */
 449         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
 450
 451         /* setup FIFO configuration registers */
 452         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 453         if (pdata->is_ar724x) {
 454                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
 455                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
 456         } else {
 457                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 458                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 459         }
 460         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 461         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 462 }
 463
 464 static void ag71xx_hw_init(struct ag71xx *ag)
 465 {
 466         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 467         u32 reset_mask = pdata->reset_bit;
 468
 469         ag71xx_hw_stop(ag);
 470
 471         if (pdata->is_ar724x) {
 472                 u32 reset_phy = reset_mask;
 473
 474                 reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
 475                 reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
 476
 477                 ar71xx_device_stop(reset_phy);
 478                 mdelay(50);
 479                 ar71xx_device_start(reset_phy);
 480                 mdelay(200);
 481         }
 482
 483         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 484         udelay(20);
 485
 486         ar71xx_device_stop(reset_mask);
 487         mdelay(100);
 488         ar71xx_device_start(reset_mask);
 489         mdelay(200);
 490
 491         ag71xx_hw_setup(ag);
 492
 493         ag71xx_dma_reset(ag);
 494 }
 495
 496 static void ag71xx_fast_reset(struct ag71xx *ag)
 497 {
 498         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 499         struct net_device *dev = ag->dev;
 500         u32 reset_mask = pdata->reset_bit;
 501         u32 rx_ds, tx_ds;
 502         u32 mii_reg;
 503
 504         reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC;
 505
 506         mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
 507         rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
 508         tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
 509
 510         ar71xx_device_stop(reset_mask);
 511         udelay(10);
 512         ar71xx_device_start(reset_mask);
 513         udelay(10);
 514
 515         ag71xx_dma_reset(ag);
 516         ag71xx_hw_setup(ag);
 517
 518         ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
 519         ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
 520         ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
 521
 522         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 523 }
 524
 525 static void ag71xx_hw_start(struct ag71xx *ag)
 526 {
 527         /* start RX engine */
 528         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 529
 530         /* enable interrupts */
 531         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 532 }
 533
 534 void ag71xx_link_adjust(struct ag71xx *ag)
 535 {
 536         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 537         u32 cfg2;
 538         u32 ifctl;
 539         u32 fifo5;
 540         u32 mii_speed;
 541
 542         if (!ag->link) {
 543                 ag71xx_hw_stop(ag);
 544                 netif_carrier_off(ag->dev);
 545                 if (netif_msg_link(ag))
 546                         printk(KERN_INFO "%s: link down\n", ag->dev->name);
 547                 return;
 548         }
 549
 550         if (pdata->is_ar724x)
 551                 ag71xx_fast_reset(ag);
 552
 553         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
 554         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
 555         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
 556
 557         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
 558         ifctl &= ~(MAC_IFCTL_SPEED);
 559
 560         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 561         fifo5 &= ~FIFO_CFG5_BM;
 562
 563         switch (ag->speed) {
 564         case SPEED_1000:
 565                 mii_speed =  MII_CTRL_SPEED_1000;
 566                 cfg2 |= MAC_CFG2_IF_1000;
 567                 fifo5 |= FIFO_CFG5_BM;
 568                 break;
 569         case SPEED_100:
 570                 mii_speed = MII_CTRL_SPEED_100;
 571                 cfg2 |= MAC_CFG2_IF_10_100;
 572                 ifctl |= MAC_IFCTL_SPEED;
 573                 break;
 574         case SPEED_10:
 575                 mii_speed = MII_CTRL_SPEED_10;
 576                 cfg2 |= MAC_CFG2_IF_10_100;
 577                 break;
 578         default:
 579                 BUG();
 580                 return;
 581         }
 582
 583         if (pdata->is_ar91xx)
 584                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
 585         else if (pdata->is_ar724x)
 586                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
 587         else
 588                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
 589
 590         if (pdata->set_pll)
 591                 pdata->set_pll(ag->speed);
 592
 593         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
 594
 595         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 596         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 597         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 598         ag71xx_hw_start(ag);
 599
 600         netif_carrier_on(ag->dev);
 601         if (netif_msg_link(ag))
 602                 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
 603                         ag->dev->name,
 604                         ag71xx_speed_str(ag),
 605                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 606
 607         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
 608                 ag->dev->name,
 609                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
 610                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
 611                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
 612
 613         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
 614                 ag->dev->name,
 615                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
 616                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
 617                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
 618
 619         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
 620                 ag->dev->name,
 621                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
 622                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
 623                 ag71xx_mii_ctrl_rr(ag));
 624 }
 625
 626 static int ag71xx_open(struct net_device *dev)
 627 {
 628         struct ag71xx *ag = netdev_priv(dev);
 629         int ret;
 630
 631         ret = ag71xx_rings_init(ag);
 632         if (ret)
 633                 goto err;
 634
 635         napi_enable(&ag->napi);
 636
 637         netif_carrier_off(dev);
 638         ag71xx_phy_start(ag);
 639
 640         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 641         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 642
 643         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 644
 645         netif_start_queue(dev);
 646
 647         return 0;
 648
 649 err:
 650         ag71xx_rings_cleanup(ag);
 651         return ret;
 652 }
 653
 654 static int ag71xx_stop(struct net_device *dev)
 655 {
 656         struct ag71xx *ag = netdev_priv(dev);
 657         unsigned long flags;
 658
 659         netif_carrier_off(dev);
 660         ag71xx_phy_stop(ag);
 661
 662         spin_lock_irqsave(&ag->lock, flags);
 663
 664         netif_stop_queue(dev);
 665
 666         ag71xx_hw_stop(ag);
 667         ag71xx_dma_reset(ag);
 668
 669         napi_disable(&ag->napi);
 670         del_timer_sync(&ag->oom_timer);
 671
 672         spin_unlock_irqrestore(&ag->lock, flags);
 673
 674         ag71xx_rings_cleanup(ag);
 675
 676         return 0;
 677 }
 678
 679 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 680                                           struct net_device *dev)
 681 {
 682         struct ag71xx *ag = netdev_priv(dev);
 683         struct ag71xx_ring *ring = &ag->tx_ring;
 684         struct ag71xx_desc *desc;
 685         dma_addr_t dma_addr;
 686         int i;
 687
 688         i = ring->curr % AG71XX_TX_RING_SIZE;
 689         desc = ring->buf[i].desc;
 690
 691         if (!ag71xx_desc_empty(desc))
 692                 goto err_drop;
 693
 694         if (ag71xx_has_ar8216(ag))
 695                 ag71xx_add_ar8216_header(ag, skb);
 696
 697         if (skb->len <= 0) {
 698                 DBG("%s: packet len is too small\n", ag->dev->name);
 699                 goto err_drop;
 700         }
 701
 702         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 703                                   DMA_TO_DEVICE);
 704
 705         ring->buf[i].skb = skb;
 706         ring->buf[i].timestamp = jiffies;
 707
 708         /* setup descriptor fields */
 709         desc->data = (u32) dma_addr;
 710         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 711
 712         /* flush descriptor */
 713         wmb();
 714
 715         ring->curr++;
 716         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
 717                 DBG("%s: tx queue full\n", ag->dev->name);
 718                 netif_stop_queue(dev);
 719         }
 720
 721         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 722
 723         /* enable TX engine */
 724         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 725
 726         return NETDEV_TX_OK;
 727
 728 err_drop:
 729         dev->stats.tx_dropped++;
 730
 731         dev_kfree_skb(skb);
 732         return NETDEV_TX_OK;
 733 }
 734
 735 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 736 {
 737         struct ag71xx *ag = netdev_priv(dev);
 738         int ret;
 739
 740         switch (cmd) {
 741         case SIOCETHTOOL:
 742                 if (ag->phy_dev == NULL)
 743                         break;
 744
 745                 spin_lock_irq(&ag->lock);
 746                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 747                 spin_unlock_irq(&ag->lock);
 748                 return ret;
 749
 750         case SIOCSIFHWADDR:
 751                 if (copy_from_user
 752                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 753                         return -EFAULT;
 754                 return 0;
 755
 756         case SIOCGIFHWADDR:
 757                 if (copy_to_user
 758                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 759                         return -EFAULT;
 760                 return 0;
 761
 762         case SIOCGMIIPHY:
 763         case SIOCGMIIREG:
 764         case SIOCSMIIREG:
 765                 if (ag->phy_dev == NULL)
 766                         break;
 767
 768                 return phy_mii_ioctl(ag->phy_dev, if_mii(ifr), cmd);
 769
 770         default:
 771                 break;
 772         }
 773
 774         return -EOPNOTSUPP;
 775 }
 776
 777 static void ag71xx_oom_timer_handler(unsigned long data)
 778 {
 779         struct net_device *dev = (struct net_device *) data;
 780         struct ag71xx *ag = netdev_priv(dev);
 781
 782         napi_schedule(&ag->napi);
 783 }
 784
 785 static void ag71xx_tx_timeout(struct net_device *dev)
 786 {
 787         struct ag71xx *ag = netdev_priv(dev);
 788
 789         if (netif_msg_tx_err(ag))
 790                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
 791
 792         schedule_work(&ag->restart_work);
 793 }
 794
 795 static void ag71xx_restart_work_func(struct work_struct *work)
 796 {
 797         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 798
 799         if (ag71xx_get_pdata(ag)->is_ar724x) {
 800                 ag->link = 0;
 801                 ag71xx_link_adjust(ag);
 802                 return;
 803         }
 804
 805         ag71xx_stop(ag->dev);
 806         ag71xx_open(ag->dev);
 807 }
 808
 809 static int ag71xx_tx_packets(struct ag71xx *ag)
 810 {
 811         struct ag71xx_ring *ring = &ag->tx_ring;
 812         int sent;
 813
 814         DBG("%s: processing TX ring\n", ag->dev->name);
 815
 816         sent = 0;
 817         while (ring->dirty != ring->curr) {
 818                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
 819                 struct ag71xx_desc *desc = ring->buf[i].desc;
 820                 struct sk_buff *skb = ring->buf[i].skb;
 821
 822                 if (!ag71xx_desc_empty(desc))
 823                         break;
 824
 825                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 826
 827                 ag->dev->stats.tx_bytes += skb->len;
 828                 ag->dev->stats.tx_packets++;
 829
 830                 dev_kfree_skb_any(skb);
 831                 ring->buf[i].skb = NULL;
 832
 833                 ring->dirty++;
 834                 sent++;
 835         }
 836
 837         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 838
 839         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
 840                 netif_wake_queue(ag->dev);
 841
 842         return sent;
 843 }
 844
 845 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 846 {
 847         struct net_device *dev = ag->dev;
 848         struct ag71xx_ring *ring = &ag->rx_ring;
 849         int done = 0;
 850
 851         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 852                         dev->name, limit, ring->curr, ring->dirty);
 853
 854         while (done < limit) {
 855                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
 856                 struct ag71xx_desc *desc = ring->buf[i].desc;
 857                 struct sk_buff *skb;
 858                 int pktlen;
 859                 int err = 0;
 860
 861                 if (ag71xx_desc_empty(desc))
 862                         break;
 863
 864                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
 865                         ag71xx_assert(0);
 866                         break;
 867                 }
 868
 869                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 870
 871                 skb = ring->buf[i].skb;
 872                 pktlen = ag71xx_desc_pktlen(desc);
 873                 pktlen -= ETH_FCS_LEN;
 874
 875                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
 876                                  AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 877
 878                 dev->last_rx = jiffies;
 879                 dev->stats.rx_packets++;
 880                 dev->stats.rx_bytes += pktlen;
 881
 882                 skb_put(skb, pktlen);
 883                 if (ag71xx_has_ar8216(ag))
 884                         err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
 885
 886                 if (err) {
 887                         dev->stats.rx_dropped++;
 888                         kfree_skb(skb);
 889                 } else {
 890                         skb->dev = dev;
 891                         skb->ip_summed = CHECKSUM_NONE;
 892                         if (ag->phy_dev) {
 893                                 ag->phy_dev->netif_receive_skb(skb);
 894                         } else {
 895                                 skb->protocol = eth_type_trans(skb, dev);
 896                                 netif_receive_skb(skb);
 897                         }
 898                 }
 899
 900                 ring->buf[i].skb = NULL;
 901                 done++;
 902
 903                 ring->curr++;
 904         }
 905
 906         ag71xx_ring_rx_refill(ag);
 907
 908         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 909                 dev->name, ring->curr, ring->dirty, done);
 910
 911         return done;
 912 }
 913
 914 static int ag71xx_poll(struct napi_struct *napi, int limit)
 915 {
 916         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 917         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 918         struct net_device *dev = ag->dev;
 919         struct ag71xx_ring *rx_ring;
 920         unsigned long flags;
 921         u32 status;
 922         int tx_done;
 923         int rx_done;
 924
 925         pdata->ddr_flush();
 926         tx_done = ag71xx_tx_packets(ag);
 927
 928         DBG("%s: processing RX ring\n", dev->name);
 929         rx_done = ag71xx_rx_packets(ag, limit);
 930
 931         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
 932
 933         rx_ring = &ag->rx_ring;
 934         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
 935                 goto oom;
 936
 937         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 938         if (unlikely(status & RX_STATUS_OF)) {
 939                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 940                 dev->stats.rx_fifo_errors++;
 941
 942                 /* restart RX */
 943                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 944         }
 945
 946         if (rx_done < limit) {
 947                 if (status & RX_STATUS_PR)
 948                         goto more;
 949
 950                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 951                 if (status & TX_STATUS_PS)
 952                         goto more;
 953
 954                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 955                         dev->name, rx_done, tx_done, limit);
 956
 957                 napi_complete(napi);
 958
 959                 /* enable interrupts */
 960                 spin_lock_irqsave(&ag->lock, flags);
 961                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 962                 spin_unlock_irqrestore(&ag->lock, flags);
 963                 return rx_done;
 964         }
 965
 966 more:
 967         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
 968                         dev->name, rx_done, tx_done, limit);
 969         return rx_done;
 970
 971 oom:
 972         if (netif_msg_rx_err(ag))
 973                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
 974
 975         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 976         napi_complete(napi);
 977         return 0;
 978 }
 979
 980 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
 981 {
 982         struct net_device *dev = dev_id;
 983         struct ag71xx *ag = netdev_priv(dev);
 984         u32 status;
 985
 986         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
 987         ag71xx_dump_intr(ag, "raw", status);
 988
 989         if (unlikely(!status))
 990                 return IRQ_NONE;
 991
 992         if (unlikely(status & AG71XX_INT_ERR)) {
 993                 if (status & AG71XX_INT_TX_BE) {
 994                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
 995                         dev_err(&dev->dev, "TX BUS error\n");
 996                 }
 997                 if (status & AG71XX_INT_RX_BE) {
 998                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
 999                         dev_err(&dev->dev, "RX BUS error\n");
1000                 }
1001         }
1002
1003         if (likely(status & AG71XX_INT_POLL)) {
1004                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1005                 DBG("%s: enable polling mode\n", dev->name);
1006                 napi_schedule(&ag->napi);
1007         }
1008
1009         ag71xx_debugfs_update_int_stats(ag, status);
1010
1011         return IRQ_HANDLED;
1012 }
1013
1014 static void ag71xx_set_multicast_list(struct net_device *dev)
1015 {
1016         /* TODO */
1017 }
1018
1019 #ifdef CONFIG_NET_POLL_CONTROLLER
1020 /*
1021  * Polling 'interrupt' - used by things like netconsole to send skbs
1022  * without having to re-enable interrupts. It's not called while
1023  * the interrupt routine is executing.
1024  */
1025 static void ag71xx_netpoll(struct net_device *dev)
1026 {
1027         disable_irq(dev->irq);
1028         ag71xx_interrupt(dev->irq, dev);
1029         enable_irq(dev->irq);
1030 }
1031 #endif
1032
1033 static const struct net_device_ops ag71xx_netdev_ops = {
1034         .ndo_open               = ag71xx_open,
1035         .ndo_stop               = ag71xx_stop,
1036         .ndo_start_xmit         = ag71xx_hard_start_xmit,
1037         .ndo_set_multicast_list = ag71xx_set_multicast_list,
1038         .ndo_do_ioctl           = ag71xx_do_ioctl,
1039         .ndo_tx_timeout         = ag71xx_tx_timeout,
1040         .ndo_change_mtu         = eth_change_mtu,
1041         .ndo_set_mac_address    = eth_mac_addr,
1042         .ndo_validate_addr      = eth_validate_addr,
1043 #ifdef CONFIG_NET_POLL_CONTROLLER
1044         .ndo_poll_controller    = ag71xx_netpoll,
1045 #endif
1046 };
1047
1048 static int __devinit ag71xx_probe(struct platform_device *pdev)
1049 {
1050         struct net_device *dev;
1051         struct resource *res;
1052         struct ag71xx *ag;
1053         struct ag71xx_platform_data *pdata;
1054         int err;
1055
1056         pdata = pdev->dev.platform_data;
1057         if (!pdata) {
1058                 dev_err(&pdev->dev, "no platform data specified\n");
1059                 err = -ENXIO;
1060                 goto err_out;
1061         }
1062
1063         if (pdata->mii_bus_dev == NULL) {
1064                 dev_err(&pdev->dev, "no MII bus device specified\n");
1065                 err = -EINVAL;
1066                 goto err_out;
1067         }
1068
1069         dev = alloc_etherdev(sizeof(*ag));
1070         if (!dev) {
1071                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1072                 err = -ENOMEM;
1073                 goto err_out;
1074         }
1075
1076         SET_NETDEV_DEV(dev, &pdev->dev);
1077
1078         ag = netdev_priv(dev);
1079         ag->pdev = pdev;
1080         ag->dev = dev;
1081         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1082                                         AG71XX_DEFAULT_MSG_ENABLE);
1083         spin_lock_init(&ag->lock);
1084
1085         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1086         if (!res) {
1087                 dev_err(&pdev->dev, "no mac_base resource found\n");
1088                 err = -ENXIO;
1089                 goto err_out;
1090         }
1091
1092         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1093         if (!ag->mac_base) {
1094                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1095                 err = -ENOMEM;
1096                 goto err_free_dev;
1097         }
1098
1099         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1100         if (!res) {
1101                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1102                 err = -ENXIO;
1103                 goto err_unmap_base;
1104         }
1105
1106         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1107         if (!ag->mii_ctrl) {
1108                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1109                 err = -ENOMEM;
1110                 goto err_unmap_base;
1111         }
1112
1113         dev->irq = platform_get_irq(pdev, 0);
1114         err = request_irq(dev->irq, ag71xx_interrupt,
1115                           IRQF_DISABLED,
1116                           dev->name, dev);
1117         if (err) {
1118                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1119                 goto err_unmap_mii_ctrl;
1120         }
1121
1122         dev->base_addr = (unsigned long)ag->mac_base;
1123         dev->netdev_ops = &ag71xx_netdev_ops;
1124         dev->ethtool_ops = &ag71xx_ethtool_ops;
1125
1126         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1127
1128         init_timer(&ag->oom_timer);
1129         ag->oom_timer.data = (unsigned long) dev;
1130         ag->oom_timer.function = ag71xx_oom_timer_handler;
1131
1132         ag->stop_desc = dma_alloc_coherent(NULL,
1133                 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1134
1135         if (!ag->stop_desc)
1136                 goto err_free_irq;
1137
1138         ag->stop_desc->data = 0;
1139         ag->stop_desc->ctrl = 0;
1140         ag->stop_desc->next = (u32) ag->stop_desc_dma;
1141
1142         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1143
1144         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1145
1146         err = register_netdev(dev);
1147         if (err) {
1148                 dev_err(&pdev->dev, "unable to register net device\n");
1149                 goto err_free_desc;
1150         }
1151
1152         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1153                dev->name, dev->base_addr, dev->irq);
1154
1155         ag71xx_dump_regs(ag);
1156
1157         ag71xx_hw_init(ag);
1158
1159         ag71xx_dump_regs(ag);
1160
1161         err = ag71xx_phy_connect(ag);
1162         if (err)
1163                 goto err_unregister_netdev;
1164
1165         err = ag71xx_debugfs_init(ag);
1166         if (err)
1167                 goto err_phy_disconnect;
1168
1169         platform_set_drvdata(pdev, dev);
1170
1171         return 0;
1172
1173 err_phy_disconnect:
1174         ag71xx_phy_disconnect(ag);
1175 err_unregister_netdev:
1176         unregister_netdev(dev);
1177 err_free_desc:
1178         dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1179                           ag->stop_desc_dma);
1180 err_free_irq:
1181         free_irq(dev->irq, dev);
1182 err_unmap_mii_ctrl:
1183         iounmap(ag->mii_ctrl);
1184 err_unmap_base:
1185         iounmap(ag->mac_base);
1186 err_free_dev:
1187         kfree(dev);
1188 err_out:
1189         platform_set_drvdata(pdev, NULL);
1190         return err;
1191 }
1192
1193 static int __devexit ag71xx_remove(struct platform_device *pdev)
1194 {
1195         struct net_device *dev = platform_get_drvdata(pdev);
1196
1197         if (dev) {
1198                 struct ag71xx *ag = netdev_priv(dev);
1199
1200                 ag71xx_debugfs_exit(ag);
1201                 ag71xx_phy_disconnect(ag);
1202                 unregister_netdev(dev);
1203                 free_irq(dev->irq, dev);
1204                 iounmap(ag->mii_ctrl);
1205                 iounmap(ag->mac_base);
1206                 kfree(dev);
1207                 platform_set_drvdata(pdev, NULL);
1208         }
1209
1210         return 0;
1211 }
1212
1213 static struct platform_driver ag71xx_driver = {
1214         .probe          = ag71xx_probe,
1215         .remove         = __exit_p(ag71xx_remove),
1216         .driver = {
1217                 .name   = AG71XX_DRV_NAME,
1218         }
1219 };
1220
1221 static int __init ag71xx_module_init(void)
1222 {
1223         int ret;
1224
1225         ret = ag71xx_debugfs_root_init();
1226         if (ret)
1227                 goto err_out;
1228
1229         ret = ag71xx_mdio_driver_init();
1230         if (ret)
1231                 goto err_debugfs_exit;
1232
1233         ret = platform_driver_register(&ag71xx_driver);
1234         if (ret)
1235                 goto err_mdio_exit;
1236
1237         return 0;
1238
1239 err_mdio_exit:
1240         ag71xx_mdio_driver_exit();
1241 err_debugfs_exit:
1242         ag71xx_debugfs_root_exit();
1243 err_out:
1244         return ret;
1245 }
1246
1247 static void __exit ag71xx_module_exit(void)
1248 {
1249         platform_driver_unregister(&ag71xx_driver);
1250         ag71xx_mdio_driver_exit();
1251         ag71xx_debugfs_root_exit();
1252 }
1253
1254 module_init(ag71xx_module_init);
1255 module_exit(ag71xx_module_exit);
1256
1257 MODULE_VERSION(AG71XX_DRV_VERSION);
1258 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1259 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1260 MODULE_LICENSE("GPL v2");
1261 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);