2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level = -1;
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
46 static void ag71xx_dump_regs(struct ag71xx *ag)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
106 ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
115 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
121 for (i = 0; i < size; i++) {
122 int idx = i * ring->desc_size;
123 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
124 DBG("ag71xx: ring %p, desc %d at %p\n",
125 ring, i, ring->buf[i].desc);
134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
136 struct ag71xx_ring *ring = &ag->tx_ring;
137 struct net_device *dev = ag->dev;
139 while (ring->curr != ring->dirty) {
140 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
142 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143 ring->buf[i].desc->ctrl = 0;
144 dev->stats.tx_errors++;
147 if (ring->buf[i].skb)
148 dev_kfree_skb_any(ring->buf[i].skb);
150 ring->buf[i].skb = NULL;
155 /* flush descriptors */
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
162 struct ag71xx_ring *ring = &ag->tx_ring;
165 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
166 ring->buf[i].desc->next = (u32) (ring->descs_dma +
167 ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
169 ring->buf[i].desc->ctrl = DESC_EMPTY;
170 ring->buf[i].skb = NULL;
173 /* flush descriptors */
180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
182 struct ag71xx_ring *ring = &ag->rx_ring;
188 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
189 if (ring->buf[i].skb) {
190 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
191 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
192 kfree_skb(ring->buf[i].skb);
196 static int ag71xx_rx_reserve(struct ag71xx *ag)
200 if (ag71xx_get_pdata(ag)->is_ar724x) {
201 if (!ag71xx_has_ar8216(ag))
205 reserve += 4 - (ag->phy_dev->pkt_align % 4);
210 return reserve + AG71XX_RX_PKT_RESERVE;
214 static int ag71xx_ring_rx_init(struct ag71xx *ag)
216 struct ag71xx_ring *ring = &ag->rx_ring;
217 unsigned int reserve = ag71xx_rx_reserve(ag);
222 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
223 ring->buf[i].desc->next = (u32) (ring->descs_dma +
224 ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
226 DBG("ag71xx: RX desc at %p, next is %08x\n",
228 ring->buf[i].desc->next);
231 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
235 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
242 skb_reserve(skb, reserve);
244 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
247 ring->buf[i].skb = skb;
248 ring->buf[i].dma_addr = dma_addr;
249 ring->buf[i].desc->data = (u32) dma_addr;
250 ring->buf[i].desc->ctrl = DESC_EMPTY;
253 /* flush descriptors */
262 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
264 struct ag71xx_ring *ring = &ag->rx_ring;
265 unsigned int reserve = ag71xx_rx_reserve(ag);
269 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
272 i = ring->dirty % AG71XX_RX_RING_SIZE;
274 if (ring->buf[i].skb == NULL) {
278 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
282 skb_reserve(skb, reserve);
285 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
289 ring->buf[i].skb = skb;
290 ring->buf[i].dma_addr = dma_addr;
291 ring->buf[i].desc->data = (u32) dma_addr;
294 ring->buf[i].desc->ctrl = DESC_EMPTY;
298 /* flush descriptors */
301 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
306 static int ag71xx_rings_init(struct ag71xx *ag)
310 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
314 ag71xx_ring_tx_init(ag);
316 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
320 ret = ag71xx_ring_rx_init(ag);
324 static void ag71xx_rings_cleanup(struct ag71xx *ag)
326 ag71xx_ring_rx_clean(ag);
327 ag71xx_ring_free(&ag->rx_ring);
329 ag71xx_ring_tx_clean(ag);
330 ag71xx_ring_free(&ag->tx_ring);
333 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
347 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
351 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
352 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
354 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
356 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
357 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
360 static void ag71xx_dma_reset(struct ag71xx *ag)
365 ag71xx_dump_dma_regs(ag);
368 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
369 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
372 * give the hardware some time to really stop all rx/tx activity
373 * clearing the descriptors too early causes random memory corruption
377 /* clear descriptor addresses */
378 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
379 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
381 /* clear pending RX/TX interrupts */
382 for (i = 0; i < 256; i++) {
383 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
384 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
387 /* clear pending errors */
388 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
389 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
391 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
393 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
396 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
398 /* mask out reserved bits */
402 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
405 ag71xx_dump_dma_regs(ag);
408 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
409 MAC_CFG1_SRX | MAC_CFG1_STX)
411 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
413 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
414 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
415 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
416 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
417 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
420 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
421 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
422 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
423 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
424 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
425 FIFO_CFG5_17 | FIFO_CFG5_SF)
427 static void ag71xx_hw_stop(struct ag71xx *ag)
429 /* disable all interrupts and stop the rx engine */
430 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
431 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
434 static void ag71xx_hw_init(struct ag71xx *ag)
436 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
437 u32 reset_mask = pdata->reset_bit;
441 if (pdata->is_ar724x) {
442 u32 reset_phy = reset_mask;
444 reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
445 reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
447 ar71xx_device_stop(reset_phy);
449 ar71xx_device_start(reset_phy);
453 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
456 ar71xx_device_stop(pdata->reset_bit);
458 ar71xx_device_start(pdata->reset_bit);
461 /* setup MAC configuration registers */
462 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
464 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
465 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
467 /* setup max frame length */
468 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
470 /* setup MII interface type */
471 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
473 /* setup FIFO configuration registers */
474 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
475 if (pdata->is_ar724x) {
476 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
477 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
479 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
480 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
482 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
483 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
485 ag71xx_dma_reset(ag);
488 static void ag71xx_hw_start(struct ag71xx *ag)
490 /* start RX engine */
491 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
493 /* enable interrupts */
494 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
497 void ag71xx_link_adjust(struct ag71xx *ag)
499 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
507 netif_carrier_off(ag->dev);
508 if (netif_msg_link(ag))
509 printk(KERN_INFO "%s: link down\n", ag->dev->name);
513 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
514 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
515 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
517 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
518 ifctl &= ~(MAC_IFCTL_SPEED);
520 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
521 fifo5 &= ~FIFO_CFG5_BM;
525 mii_speed = MII_CTRL_SPEED_1000;
526 cfg2 |= MAC_CFG2_IF_1000;
527 fifo5 |= FIFO_CFG5_BM;
530 mii_speed = MII_CTRL_SPEED_100;
531 cfg2 |= MAC_CFG2_IF_10_100;
532 ifctl |= MAC_IFCTL_SPEED;
535 mii_speed = MII_CTRL_SPEED_10;
536 cfg2 |= MAC_CFG2_IF_10_100;
543 if (pdata->is_ar91xx)
544 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
545 else if (pdata->is_ar724x)
546 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
548 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
551 pdata->set_pll(ag->speed);
553 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
555 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
556 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
557 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
560 netif_carrier_on(ag->dev);
561 if (netif_msg_link(ag))
562 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
564 ag71xx_speed_str(ag),
565 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
567 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
569 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
570 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
571 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
573 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
575 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
576 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
577 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
579 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
581 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
582 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
583 ag71xx_mii_ctrl_rr(ag));
586 static int ag71xx_open(struct net_device *dev)
588 struct ag71xx *ag = netdev_priv(dev);
591 ret = ag71xx_rings_init(ag);
595 napi_enable(&ag->napi);
597 netif_carrier_off(dev);
598 ag71xx_phy_start(ag);
600 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
601 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
603 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
605 netif_start_queue(dev);
610 ag71xx_rings_cleanup(ag);
614 static int ag71xx_stop(struct net_device *dev)
616 struct ag71xx *ag = netdev_priv(dev);
619 netif_carrier_off(dev);
622 spin_lock_irqsave(&ag->lock, flags);
624 netif_stop_queue(dev);
627 ag71xx_dma_reset(ag);
629 napi_disable(&ag->napi);
630 del_timer_sync(&ag->oom_timer);
632 spin_unlock_irqrestore(&ag->lock, flags);
634 ag71xx_rings_cleanup(ag);
639 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
640 struct net_device *dev)
642 struct ag71xx *ag = netdev_priv(dev);
643 struct ag71xx_ring *ring = &ag->tx_ring;
644 struct ag71xx_desc *desc;
648 i = ring->curr % AG71XX_TX_RING_SIZE;
649 desc = ring->buf[i].desc;
651 if (!ag71xx_desc_empty(desc))
654 if (ag71xx_has_ar8216(ag))
655 ag71xx_add_ar8216_header(ag, skb);
658 DBG("%s: packet len is too small\n", ag->dev->name);
662 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
665 ring->buf[i].skb = skb;
666 ring->buf[i].timestamp = jiffies;
668 /* setup descriptor fields */
669 desc->data = (u32) dma_addr;
670 desc->ctrl = (skb->len & DESC_PKTLEN_M);
672 /* flush descriptor */
676 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
677 DBG("%s: tx queue full\n", ag->dev->name);
678 netif_stop_queue(dev);
681 DBG("%s: packet injected into TX queue\n", ag->dev->name);
683 /* enable TX engine */
684 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
689 dev->stats.tx_dropped++;
695 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
697 struct ag71xx *ag = netdev_priv(dev);
702 if (ag->phy_dev == NULL)
705 spin_lock_irq(&ag->lock);
706 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
707 spin_unlock_irq(&ag->lock);
712 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
718 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
725 if (ag->phy_dev == NULL)
728 return phy_mii_ioctl(ag->phy_dev, if_mii(ifr), cmd);
737 static void ag71xx_oom_timer_handler(unsigned long data)
739 struct net_device *dev = (struct net_device *) data;
740 struct ag71xx *ag = netdev_priv(dev);
742 napi_schedule(&ag->napi);
745 static void ag71xx_tx_timeout(struct net_device *dev)
747 struct ag71xx *ag = netdev_priv(dev);
749 if (netif_msg_tx_err(ag))
750 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
752 schedule_work(&ag->restart_work);
755 static void ag71xx_restart_work_func(struct work_struct *work)
757 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
759 ag71xx_stop(ag->dev);
760 ag71xx_open(ag->dev);
763 static int ag71xx_tx_packets(struct ag71xx *ag)
765 struct ag71xx_ring *ring = &ag->tx_ring;
768 DBG("%s: processing TX ring\n", ag->dev->name);
771 while (ring->dirty != ring->curr) {
772 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
773 struct ag71xx_desc *desc = ring->buf[i].desc;
774 struct sk_buff *skb = ring->buf[i].skb;
776 if (!ag71xx_desc_empty(desc))
779 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
781 ag->dev->stats.tx_bytes += skb->len;
782 ag->dev->stats.tx_packets++;
784 dev_kfree_skb_any(skb);
785 ring->buf[i].skb = NULL;
791 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
793 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
794 netif_wake_queue(ag->dev);
799 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
801 struct net_device *dev = ag->dev;
802 struct ag71xx_ring *ring = &ag->rx_ring;
805 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
806 dev->name, limit, ring->curr, ring->dirty);
808 while (done < limit) {
809 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
810 struct ag71xx_desc *desc = ring->buf[i].desc;
815 if (ag71xx_desc_empty(desc))
818 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
823 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
825 skb = ring->buf[i].skb;
826 pktlen = ag71xx_desc_pktlen(desc);
827 pktlen -= ETH_FCS_LEN;
829 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
830 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
832 dev->last_rx = jiffies;
833 dev->stats.rx_packets++;
834 dev->stats.rx_bytes += pktlen;
836 skb_put(skb, pktlen);
837 if (ag71xx_has_ar8216(ag))
838 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
841 dev->stats.rx_dropped++;
845 skb->ip_summed = CHECKSUM_NONE;
847 ag->phy_dev->netif_receive_skb(skb);
849 skb->protocol = eth_type_trans(skb, dev);
850 netif_receive_skb(skb);
854 ring->buf[i].skb = NULL;
860 ag71xx_ring_rx_refill(ag);
862 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
863 dev->name, ring->curr, ring->dirty, done);
868 static int ag71xx_poll(struct napi_struct *napi, int limit)
870 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
871 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
872 struct net_device *dev = ag->dev;
873 struct ag71xx_ring *rx_ring;
880 tx_done = ag71xx_tx_packets(ag);
882 DBG("%s: processing RX ring\n", dev->name);
883 rx_done = ag71xx_rx_packets(ag, limit);
885 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
887 rx_ring = &ag->rx_ring;
888 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
891 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
892 if (unlikely(status & RX_STATUS_OF)) {
893 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
894 dev->stats.rx_fifo_errors++;
897 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
900 if (rx_done < limit) {
901 if (status & RX_STATUS_PR)
904 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
905 if (status & TX_STATUS_PS)
908 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
909 dev->name, rx_done, tx_done, limit);
913 /* enable interrupts */
914 spin_lock_irqsave(&ag->lock, flags);
915 ag71xx_int_enable(ag, AG71XX_INT_POLL);
916 spin_unlock_irqrestore(&ag->lock, flags);
921 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
922 dev->name, rx_done, tx_done, limit);
926 if (netif_msg_rx_err(ag))
927 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
929 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
934 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
936 struct net_device *dev = dev_id;
937 struct ag71xx *ag = netdev_priv(dev);
940 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
941 ag71xx_dump_intr(ag, "raw", status);
943 if (unlikely(!status))
946 if (unlikely(status & AG71XX_INT_ERR)) {
947 if (status & AG71XX_INT_TX_BE) {
948 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
949 dev_err(&dev->dev, "TX BUS error\n");
951 if (status & AG71XX_INT_RX_BE) {
952 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
953 dev_err(&dev->dev, "RX BUS error\n");
957 if (likely(status & AG71XX_INT_POLL)) {
958 ag71xx_int_disable(ag, AG71XX_INT_POLL);
959 DBG("%s: enable polling mode\n", dev->name);
960 napi_schedule(&ag->napi);
963 ag71xx_debugfs_update_int_stats(ag, status);
968 static void ag71xx_set_multicast_list(struct net_device *dev)
973 #ifdef CONFIG_NET_POLL_CONTROLLER
975 * Polling 'interrupt' - used by things like netconsole to send skbs
976 * without having to re-enable interrupts. It's not called while
977 * the interrupt routine is executing.
979 static void ag71xx_netpoll(struct net_device *dev)
981 disable_irq(dev->irq);
982 ag71xx_interrupt(dev->irq, dev);
983 enable_irq(dev->irq);
987 static const struct net_device_ops ag71xx_netdev_ops = {
988 .ndo_open = ag71xx_open,
989 .ndo_stop = ag71xx_stop,
990 .ndo_start_xmit = ag71xx_hard_start_xmit,
991 .ndo_set_multicast_list = ag71xx_set_multicast_list,
992 .ndo_do_ioctl = ag71xx_do_ioctl,
993 .ndo_tx_timeout = ag71xx_tx_timeout,
994 .ndo_change_mtu = eth_change_mtu,
995 .ndo_set_mac_address = eth_mac_addr,
996 .ndo_validate_addr = eth_validate_addr,
997 #ifdef CONFIG_NET_POLL_CONTROLLER
998 .ndo_poll_controller = ag71xx_netpoll,
1002 static int __devinit ag71xx_probe(struct platform_device *pdev)
1004 struct net_device *dev;
1005 struct resource *res;
1007 struct ag71xx_platform_data *pdata;
1010 pdata = pdev->dev.platform_data;
1012 dev_err(&pdev->dev, "no platform data specified\n");
1017 if (pdata->mii_bus_dev == NULL) {
1018 dev_err(&pdev->dev, "no MII bus device specified\n");
1023 dev = alloc_etherdev(sizeof(*ag));
1025 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1030 SET_NETDEV_DEV(dev, &pdev->dev);
1032 ag = netdev_priv(dev);
1035 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1036 AG71XX_DEFAULT_MSG_ENABLE);
1037 spin_lock_init(&ag->lock);
1039 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1041 dev_err(&pdev->dev, "no mac_base resource found\n");
1046 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1047 if (!ag->mac_base) {
1048 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1053 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1055 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1057 goto err_unmap_base;
1060 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1061 if (!ag->mii_ctrl) {
1062 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1064 goto err_unmap_base;
1067 dev->irq = platform_get_irq(pdev, 0);
1068 err = request_irq(dev->irq, ag71xx_interrupt,
1072 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1073 goto err_unmap_mii_ctrl;
1076 dev->base_addr = (unsigned long)ag->mac_base;
1077 dev->netdev_ops = &ag71xx_netdev_ops;
1078 dev->ethtool_ops = &ag71xx_ethtool_ops;
1080 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1082 init_timer(&ag->oom_timer);
1083 ag->oom_timer.data = (unsigned long) dev;
1084 ag->oom_timer.function = ag71xx_oom_timer_handler;
1086 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1088 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1090 err = register_netdev(dev);
1092 dev_err(&pdev->dev, "unable to register net device\n");
1096 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1097 dev->name, dev->base_addr, dev->irq);
1099 ag71xx_dump_regs(ag);
1103 ag71xx_dump_regs(ag);
1105 err = ag71xx_phy_connect(ag);
1107 goto err_unregister_netdev;
1109 err = ag71xx_debugfs_init(ag);
1111 goto err_phy_disconnect;
1113 platform_set_drvdata(pdev, dev);
1118 ag71xx_phy_disconnect(ag);
1119 err_unregister_netdev:
1120 unregister_netdev(dev);
1122 free_irq(dev->irq, dev);
1124 iounmap(ag->mii_ctrl);
1126 iounmap(ag->mac_base);
1130 platform_set_drvdata(pdev, NULL);
1134 static int __devexit ag71xx_remove(struct platform_device *pdev)
1136 struct net_device *dev = platform_get_drvdata(pdev);
1139 struct ag71xx *ag = netdev_priv(dev);
1141 ag71xx_debugfs_exit(ag);
1142 ag71xx_phy_disconnect(ag);
1143 unregister_netdev(dev);
1144 free_irq(dev->irq, dev);
1145 iounmap(ag->mii_ctrl);
1146 iounmap(ag->mac_base);
1148 platform_set_drvdata(pdev, NULL);
1154 static struct platform_driver ag71xx_driver = {
1155 .probe = ag71xx_probe,
1156 .remove = __exit_p(ag71xx_remove),
1158 .name = AG71XX_DRV_NAME,
1162 static int __init ag71xx_module_init(void)
1166 ret = ag71xx_debugfs_root_init();
1170 ret = ag71xx_mdio_driver_init();
1172 goto err_debugfs_exit;
1174 ret = platform_driver_register(&ag71xx_driver);
1181 ag71xx_mdio_driver_exit();
1183 ag71xx_debugfs_root_exit();
1188 static void __exit ag71xx_module_exit(void)
1190 platform_driver_unregister(&ag71xx_driver);
1191 ag71xx_mdio_driver_exit();
1192 ag71xx_debugfs_root_exit();
1195 module_init(ag71xx_module_init);
1196 module_exit(ag71xx_module_exit);
1198 MODULE_VERSION(AG71XX_DRV_VERSION);
1199 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1200 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1201 MODULE_LICENSE("GPL v2");
1202 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);