4 #define AMAZON_DMA_REG32(reg_num) *((volatile u32*)(reg_num))
5 #define AMAZON_DMA_CH_STEP 4
7 #define COMB_ISR_RX_MASK 0xfe000000
8 #define COMB_ISR_TX_MASK 0x01f00000
16 #define DMA_DESC_OWN_CPU 0x0
17 #define DMA_DESC_OWN_DMA 0x80000000
18 #define DMA_DESC_CPT_SET 0x40000000
19 #define DMA_DESC_SOP_SET 0x20000000
20 #define DMA_DESC_EOP_SET 0x10000000
22 #define switch_rx_chan_base 0
23 #define switch_tx_chan_base 7
24 #define switch2_rx_chan_base 2
25 #define switch2_tx_chan_base 8
26 #define TPE_rx_chan_base 4
27 #define TPE_tx_chan_base 9
28 #define DPLus2FPI_rx_chan_base 6
29 #define DPLus2FPI_tx_chan_base 11
33 #define CHAN_TOTAL_NUM (RX_CHAN_NUM+TX_CHAN_NUM)
34 #define DEFAULT_OFFSET 20
35 #define DESCRIPTOR_SIZE 8
37 typedef struct dev_list{
38 struct dma_device_info* dev;
40 struct dev_list* prev;
41 struct dev_list* next;
44 typedef struct channel_info{
58 void* opt[DEFAULT_OFFSET];
59 u8* (*buffer_alloc)(int len,int* offset, void** opt);
60 int (*buffer_free)(u8* dataptr,void* opt);
61 int (*intr_handler)(struct dma_device_info* info,int status);
63 struct dma_device_info* dma_dev;